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參數(shù)資料
| 型號(hào)： | TECO3264 |
| 廠商： | Lineage Power |
| 英文描述： | 32-Channel Echo Canceller(32通道回波清除器) |
| 中文描述： | 32通道回聲消除器（32通道回波清除器） |
| 文件頁數(shù)： | 16/128頁 |
| 文件大小： | 2328K |
| 代理商： | TECO3264 |
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Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
16
Lucent Technologies Inc.
External Control Connection
(continued)
Microprocessor Interface and Control (MPIC)
(continued)
Microprocessor Interface
This interface provides microprocessor access to the control, provisioning, option, parameter, status, and alarm
registers, all of which are directly accessible via the address and data buses. Interrupt capability is also provided at
this interface.
1. All status and alarm registers are maskable and exercisable under microprocessor control.
2. The microprocessor has read and write access to the control, provisioning, option, parameter, and mask regis-
ters and read-only access to the status and alarm registers. Alarm registers are cleared when read by the micro-
processor. Microprocessor writes and reads at this interface are asynchronous to the clock.
3. The chip has access to the control, provisioning, option, and parameter registers and read-only access to the
status and alarm registers.
4. An interrupt signal is generated whenever any unmasked alarm condition is detected.
In order to provide flexibility in the choice of a microprocessor, two interface modes are supported. The primary
mode uses separate address and data buses, and interfaces directly with the Motorola MC68000* microprocessor
family. This mode is patterned on the microprocessor interfaces found in the T7270 Time-Slot Interchanger and
T7230 Primary Access Framer/Controller. Pin definitions for each of the modes are defined in Table 2. The I/O
specifications for these pins are defined in Table 2, Figure 3, MPIC Write Cycle (UP_MODE = 1), and Figure 4,
MPIC Read Cycle (UP_MODE = 1) for UP_MODE = 1 (Motorolamode), and Figure 5, MPIC Write Cycle
(UP_MODE = 0) and Figure 6, MPIC Read Cycle (UP_MODE = 0) for UP_MODE = 0 (Intel mode).
* MC68000is a trademark of Motorola, Inc.
* In other Inteldevices, INT may be an active-low signal, depending on the device.
Table 2. Microprocessor Interface Control I/O
Device Pin
Name
Pin
Number
Type
Microprocessor Mode
IntelMode
Motorola Mode
UP_MODE
23
I
UP_MODE = 0
UP_MODE = 1
ALE
19
I
Address Latch Enable (ALE)
(1 to 0 transition)
Not Used (ALE = 1)
D0—D7
(156—159,
2—5)
I/O
Data Bus
Data Bus
A0—A9
(6, 8—12,
14—17)
I
Address Bus
Address Bus
AS
21
I
Chip Select (CS) (active-low)
Address Strobe (active-low)
R/W
24
I
Read Cycle (RD) (active-low)
Read/Write Select
DS
22
I
Write Cycle (WR) (active-low)
Data Strobe (active-low)
DTACK
48
O
Ready (RDY for 8086 family)
(TECO3264 and Inteldevices are
active-high.)
Data Transfer Acknowledge
(TECO3264 and Motorola devices
are active-low.)
INT
49
O
Interrupt (TECO3264 is active-high,
but Intel8086 family* is active-low.)
Interrupt (TECO3264 and Motorola
devices are active-low.)
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