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| 型號(hào)： | TECO3264 |
| 廠商： | Lineage Power |
| 英文描述： | 32-Channel Echo Canceller(32通道回波清除器) |
| 中文描述： | 32通道回聲消除器（32通道回波清除器） |
| 文件頁(yè)數(shù)： | 50/128頁(yè) |
| 文件大?。?/td> | 2328K |
| 代理商： | TECO3264 |
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Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
50
Lucent Technologies Inc.
Register Architecture
(continued)
Recommended Register Values
The TECO3264 chip is supplied with a set of recommended register values. These values represent many years of
experience with a wide variety of networks and on extensive laboratory subjective and objective tests. With the rec-
ommended values, the performance of the TECO3264 should meet or exceed subjective expectations in a wide
range of network conditions. Some functions are set at system design time, such as system bit rate, time-slot and
sync alignment, and the settings affecting E1 or DS1 applications. As mentioned, there are a few parameters that
may be adjusted to compensate for problem or unusual, but systematic, network conditions, such as consistently
poor hybrid balance. New applications such as packet voice and Internet telephony are growing. New information
will be provided as it becomes available.
Recommended values are given in hexidecimal for each page 0 register and the equivalent binary values are given
for each bit in the 8-bit registers. The corresponding binary values may represent one to eight parameters per reg-
ister with one too many bits per function. A few functions take more than 8 bits and occupy parts of two or more
registers.
For most parameters that have a range of values, slight changes will have little audible effect. Many of the param-
eters interact to perform the echo cancelling function, and changes in one may require adjustment of others to
obtain the maximum available performance. Thus, most of the echo canceller register values are expected to be
set to a constant value during initialization.
Some functions are only used for chip development or for manufacturing tests of the TECO3264 chip and should
never be of concern in either system development or field applications. Some functions, such as adjusting the tim-
ing relationships among the sync pulse, clock, and data bits, are set during system design and never changed
again.
Most of the functions are set once for a given network architecture and remain the same. Examples are μ-law and
A-law coding and most echo canceller functions. A few echo canceller functions may need fine tuning if unusual
network conditions are found. An example is adjusting voice and data echo return loss thresholds when a network
is found to have poor four-to-two-wire hybrid performance. Another example is when network levels are known to
be high and the loss pads can be switched in.
Notation and Format: Bits per Parameter and Bits in Registers
Symbol names for single bit parameters are written without indication of any bit size. An example is CMS for con-
centration highway bit rate select (register 02F, bit position 0). Symbols for multibit parameters are written with an
indication in brackets of the bit length of the parameter. An example is the 8-bit parameter ADATA[7:0] for alpha
data where the parameters’ bits are numbered [7:0] (and found in register 073, bit positions 7—0). Bit 0 is the least
significant bit, and bit 7 is the most significant bit for ADATA. A colon separates the 0 and 7 bit places within the
brackets. (Note that a dash separates the bit positions when referring to registers.)
Parameters with 8 bits or less are contained within one register. Parameters with fewer than 8 bits may share a
register with other parameters. Parameters with more than 8 bits are contained in as many registers as necessary.
Per-channel parameters, such as enable bypass (clear channel) EBP, are 1-bit long but are spread with 1 bit per
register among the first 32 registers, 000—01F. All-channel parameters with more than 8 bits may be contained in
two to three registers as needed. An example is the 14-bit enable edge threshold EETHR[13:0] contained in regis-
ter 07E, bit positions 7—0, and in register 07F, bit positions 5—0. Pointers between registers containing portions of
a parameter are included in the descriptive text for the parameters in Table 24—Table 128. Tables 22 and 23 list all
the registers connected with each parameter. The registers containing parameter portions are usually, but not
always, adjacent.
Unused register bit positions are labeled as reserved and must be set to 0.
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