參數(shù)資料
型號(hào)： TECO3264
廠商： Lineage Power
英文描述： 32-Channel Echo Canceller(32通道回波清除器)
中文描述： 32通道回聲消除器（32通道回波清除器）
文件頁數(shù)： 10/128頁
文件大?。?/td> 2328K
代理商： TECO3264
Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
10
Lucent Technologies Inc.
Pin Information
(continued)
Pin Descriptions
Table 1. Pin Descriptions
* I
u
indicates an internal pull-up.
Pin
Symbol
Type
*
Description
152
153
154
69
YPCM
XPCM
XLINEAR
CK65EXT
I
I
I
I
2.048/4.096 Mbits/s Near Input Serial PCM Data Stream.
2.048/4.096 Mbits/s Far Input Serial PCM Data Stream.
4.096 Mbits/s Far Input Linear PCM from Optional Coprocessor.
External Clock @ 65.536 MHz.
This clock is primarily intended for
factory test and should be tied low for normal use.
Input Clock.
This input clock controls the rate at which information is
sent or received on both the transmit and receive PCM streams. It
operates at 8.192 MHz.
Frame Synchronization.
The rising edge of this signal, which has a
frequency of 8 kHz, marks the beginning of a data frame. The SYNC
clock can be detected on either a rising or falling edge of CK8M by
programming the frame edge (FE) register bit. Individual time slots are
determined relative to the detection of the SYNC clock. SYNC clock
should be high for a minimum of 244 ns.
External/Internal Clock Select.
A low on this pin will select the internal
65.536 MHz clock.
256 kHz Per-Channel Echo Canceller On/Off Control Stream.
(1 = on; 0 = off.)
256 kHz Per-Channel 64-Clear On/Off Control Stream.
(1 = on; 0 = off.)
256 kHz Per-Channel NLP Freeze Control Stream.
(1 = freeze; 0 = no freeze.)
256 kHz Per-Channel NLP On/Off Control Stream.
(1 = on; 0 = off.)
256 kHz Per-Channel H-Reset Control Stream.
(1 = reset; 0 = no reset.)
256 kHz Per-Channel H-Freeze Control Stream.
(1 = freeze; 0 = no freeze.)
256 kHz Per-Channel Call Boundary Control Stream.
(0
→
1 transition = call boundary event; otherwise, no call boundary
event.)
256 kHz Per-Channel Voice/Data Call Indication.
(1 = data; 0 = voice.)
Microprocessor Interface Address Latch Enable (Active-Low).
Microprocessor Interface Address Strobe (Active-Low).
Microprocessor Interface Data Strobe (Active-Low).
Microprocessor Interface Mode.
(1 = Motorola; 0 = Intel.)
Microprocessor Interface Read/Write Control.
(1 = read; 0 = write.)
67
CK8M
I
151
SYNC
I
68
CKEXT
I
26
ECDIS
I
28
ENBP
I
29
NLPFRZ
I
30
NLPEN
I
31
HRST
I
32
HFRZ
I
34
CALLB
I
35
VSC
I
19
21
22
23
24
ALE
AS
DS
UPMD
R/W
I
I
I
I
I
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