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參數(shù)資料
| 型號(hào)： | TECO3264 |
| 廠商： | Lineage Power |
| 英文描述： | 32-Channel Echo Canceller(32通道回波清除器) |
| 中文描述： | 32通道回聲消除器（32通道回波清除器） |
| 文件頁(yè)數(shù)： | 26/128頁(yè) |
| 文件大?。?/td> | 2328K |
| 代理商： | TECO3264 |
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Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
26
Lucent Technologies Inc.
External Control Connection
(continued)
PCM Input/Output (I/O) Timing and Register Control
(continued)
5-7346(F)r.1
Figure 14. SYNC Shifted to Edge of CK8M
When using all of these parameters, the suggestion is to put all channels in 64-clear mode (set registers 0—1F
equal to 02 hexadecimal) and put in a fixed, recognizable bit pattern on TS0. Then look at the output data and
adjust the parameters above until it is aligned properly. Work initially with the receive path only, and then with the
send path. Once the receive path is aligned, then apply the same offsets for the send path; X and Y should have
the same offset. Similarly, C and E should also have the same offset. Both paths should now be aligned.
Note:
In bypass mode, 8-bit data out is equal to the 8-bit data in; however, the condition of having the data aligned
in bypass mode is a necessary condition, but it is not sufficient.
Table 5—Table 8 give decimal values of CET and CER for various values of CMS, [X, Y]RCE, [X, Y]RBOFF[3:0],
[C, E]XBOFF[3:0], and [C, E]XCE.
The suggested procedure to set up the right parameters is as follows:
1.
Set up the TECO3264 in 64-clear mode for all channels but one by setting registers 0x00 = 0x02, 0x01 = 0x00,
and 0x02—0x1F to 0x02. Note that one channel is not being set to 64-clear mode. When using CMS = 1, the
control of time slots (per-channel provisioning) is shifted by one relative to registers 0—1F. Setting register
0x01 = 0x00 means echo cancellation is being enabled for time slot 0 (TS0, first time slot). By the same token,
setting register 0x00 = 0x02 means bypass mode is being enabled for time slot 31 (TS31, last time slot). The
same characteristic applies to the other time slots. For CMS = 0, there is a one-to-one correspondence
between time slots 0—31 and registers 0x00—0x1F, and user should not be concerned; TS0 corresponds to
register 00 and so on.
Start working with the receive path, meaning a test sequence is input in X and observed at C.
Enter a defined sequence pattern, i.e., 0x5B = 01011011 in time slot 0.
2.
3.
SYNC
CK8M
EET = 0
FE = 0
EET = 0
FE = 0
FE = 1 (CANNOT USE FE = 1)
SYNC
CK8M
EET = 1
EET = 1
FE = 1
FE = 1 (CANNOT USE FE = 0)
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