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參數(shù)資料
| 型號： | TECO3264 |
| 廠商： | Lineage Power |
| 英文描述： | 32-Channel Echo Canceller(32通道回波清除器) |
| 中文描述： | 32通道回聲消除器（32通道回波清除器） |
| 文件頁數(shù)： | 20/128頁 |
| 文件大小： | 2328K |
| 代理商： | TECO3264 |
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Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
20
Lucent Technologies Inc.
External Control Connection
(continued)
PCM Input/Output (I/O) Timing and Register Control
The TECO3264 has a number of configurable parameters pertaining to the PCM data, the synchronization (SYNC,
8 kHz) clock, and the input clock (8.192 MHz). The only input clock that is required is the 8.192 MHz clock—there
are no other frequency options. The PCM ports support either 4.096 Mbits/s or 2.048 Mbits/s serial data. Proper
PCM timing is controlled through the use of programmable registers. Table 14, Transmission Parameters, on page
37 gives a description of the control features necessary to establish proper data and clock synchronization.
Transmission parameters can be set to sample the data wherever it needs to work. Essentially, the user will choose
to sample the data synchronously at either 4.096 Mbits/s or 2.048 Mbits/s and the transmission parameters can
vary the phase of the sampling relative to the sync pulse. For example, in cases when the [C, E] PCM data is not
properly aligned to time slot 0 (TS0) relative to the synchronization clock, then a combination of the bit offset
parameters (CXBOFF, XRBOFF, YRBOFF, EXBOFF), the bulk time-slot delay parameters [X, Y]DLY[4:0], and the
transmit clock edge parameters [C, E]XCE can be adjusted to fix the problem. Any properly formed 2.048 Mbits/s
(or 4.096 Mbits/s) serial stream can be made to work by adjusting these parameters.
PCM I/O Frame Timing
Figure 8, SYNC and PCM Timing for DS1 and CEPT Frame illustrates the SYNC and PCM timing for both DS1 and
CEPT frame modes. In DS1 frame mode, the PCM data consists of 24 payload time slots and eight stuffed
(unused) time slots. These eight stuffed time slots can also be placed anywhere within the 2.048 Mbits/s data
stream, and they do not have to be contiguously placed. It is recommended to set the echo canceller to bypass
mode for those time slots: set those registers to hexadecimal two (0x02). In CEPT frame mode, the PCM data con-
sists of 32 payload time slots. For the 2.048 Mbits/s rate, there are 8 bits per time slot and one bit is four cycles of
the CK8M clock. For the 4.096 Mbits/s rate, there are 16 bits per time slot and one bit is two cycles of the CK8M
clock. However, only the first 8 bits of each time slot constitute valid data, unless some of the parity bit options (or
similar features, i.e., see register 0x21 bit 4 or 5) are set. Figure 9, Interface Timing (SYNC, 8 kHz) and Figure 10,
Interface Timing (CK8M Clock) show the relationship among bits, time slots, and frame synchronization for both the
2.048 Mbits/s and 4.096 Mbits/s rate.
5-7303(F)r.1
* Only the first 8 bits in each time slot are valid data.
Figure 8. SYNC and PCM Timing for DS1 and CEPT Frame
2.048 Mbits/s
PCM DATA
8 STUFFED
SLOTS
24 VALID TIME SLOTS (8 bits/TIME SLOT)
FRAME
2
32 VALID TIME SLOTS
FRAME
2
8 STUFFED
SLOTS
24 VALID TIME SLOTS (16 bits/TIME SLOT*)
FRAME
2
32 VALID TIME SLOTS (16 bits/TIME SLOT*)
SYNC
DS1 FORMAT
2.048 Mbits/s
PCM DATA
CEPT FORMAT
4.096 Mbits/s
PCM DATA
DS1 FORMAT
4.096 Mbits/s
PCM DATA
CEPT FORMAT
125
μ
s
FRAME 1
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