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參數(shù)資料
| 型號(hào)： | TECO3264 |
| 廠商： | Lineage Power |
| 英文描述： | 32-Channel Echo Canceller(32通道回波清除器) |
| 中文描述： | 32通道回聲消除器（32通道回波清除器） |
| 文件頁數(shù)： | 25/128頁 |
| 文件大?。?/td> | 2328K |
| 代理商： | TECO3264 |
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Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
25
Lucent Technologies Inc.
External Control Connection
(continued)
PCM Input/Output (I/O) Timing and Register Control
(continued)
The bit offset parameters move the PCM stream by 1 bit at the 4.096 Mbits/s rate (by 1/2 bit at the 2.048 Mbits/s
rate) in either direction when you increment or decrement the parameter value by one. For instance, if the sign bit
(for μ-law and A-law, bit 0 = sign, bit 1 = MSB, and bit 7 = LSB) of TS0 is off by 1 bit, then changing the value by
one (increment refers to right direction) will fix it. The range of the bit offset parameter will adjust the output align-
ment bit by bit within one time slot. Since the output data depends on the input data, it is important to know that
changing values in the [X, Y]RBOFF parameters will also offset the output data. Incrementing [X, Y]RBOFF by one
will move the [X, Y] PCM highway by 1 bit (to the right) and the [C, E] PCM highway by 1 bit, but in the opposite
direction. For CMS = 1, the shift is by 1/2 bit. This opposite direction behavior occurs in the output data only when
the receive bit offset parameter is changed. Figure 13, Received and Transmit Offsets Related to Received and
Transmit Data shows how the received and transmit offsets are related to the received and transmit data, respec-
tively.
5-7345(F)r.1
Note: A = any bit within the data stream.
Figure 13. Received and Transmit Offsets Related to Received and Transmit Data
The bulk time-slot delay register will move the output alignment in increments of one time slot. Therefore, for
example, if the output PCM shows up exactly one time slot early, then adding one to this value will move it out one
time slot. The transmit clock edge bit will simply change which clock edge the data is clocked out on.
The frame edge bit for sync sampling (FE, register 0x33 bit 1) samples at the positive-going/rising (FE = 1) or neg-
ative-going/falling edge (FE = 0) of the clock pulse.
The clock enable edge transfer bit for sync sampling (EET, Table 44, Edge Sampling Register (033) [02], on page
78, bit 0) allows the SYNC clock to be shifted by one edge of the CK8M clock. This is very useful in cases when the
rising edge (or falling edge) of the SYNC clock coincides with the edge of the CK8M clock where it is expected to
be sampled. Figure 14, SYNC Shifted to Edge of CK8M shows the cases when FE = 0 and EET = 0; FE = 1 and
EET = 1.
SYNC
RECEIVED DATA
TRANSMIT DATA
0
1
2
3
4
5
6
7
8
9
A2
A3
A4
A5
A6
A7
A8
A9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
TRANSMIT OFFSET = 0
RECEIVED OFFSET = 0
RECEIVED DATA
RECEIVED OFFSET = 2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
TRANSMIT DATA
TRANSMIT OFFSET = 0
TRANSMIT DATA
TRANSMIT OFFSET = 2
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