參數(shù)資料
型號： TECO3264
廠商： Lineage Power
英文描述： 32-Channel Echo Canceller(32通道回波清除器)
中文描述： 32通道回聲消除器（32通道回波清除器）
文件頁數(shù)： 37/128頁
文件大?。?/td> 2328K
代理商： TECO3264
Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
37
Lucent Technologies Inc.
Parameters
(continued)
PCM Transmission Parameters
The parameters in Table 14 relate to the flexibility of the PCM interface. They generally instruct the device as to the
I/O format of the PCM interface ports.
* See note in Bit Offset Operation section on page 22.
Table 14. Transmission Parameters
Symbol
Description
Memory Map
Starting Address (Hex)
XRCE
Receive clock edge.
0 = sample receive data on the falling edge of CK8M*.
1 = sample receive data on the rising edge of CK8M*.
X receive bit offset. These four bits provide a fixed offset, relative to
the frame-synchronization pulse (SYNC), for the first bit received in
each time slot. The offset is the number of data periods by which
reception of the first bit on [X] is delayed. All subsequent receptions of
the first bit also follow this offset. One data period (1 bit) equals to 4
cycles of CK8M for CMS = 1, and 2 cycles of CK8M for CMS = 0.
Received data is sampled in the middle of the data bit.
0x2A
XRBOFF[3:0]
0x2A
TMODE[1:0]
109-test mode.
TMODE0 = 1 send data to one channel.
TMODE1 = 1 send data to all channels.
0x2A
XPY[2:0]
X input parity detection options.
XPY0 = 1 enable parity checking; 0 = disable.
XPY1 = 1 even parity; 0 = odd parity.
XPY2 = 1 bit 8; 0 = bit 15.
0x2B
XCODEC
X input invert select (1 = inverted; 0 = noninverted).
X input A-law/
μ
-law select.
Enable use of XLINEAR linear PCM input port (active-high).
0x2E
XULAW
0x2E
AEN
0x2E
CCODEC
C output PCM invert select (1 = inverted; 0 = noninverted).
C output A-law/
μ
-law select.
C output A-law/
μ
-law adjustment.
C output parity generation options.
CPY0 = 1 enable parity generation/0 = disable.
CPY1 = 1 even parity; 0 = odd disable.
CPY2 = 1 bit 8; 0 = bit 15.
C transmit bit offset. These 4 bits provide a fixed offset, relative to the
frame-synchronization pulse (SYNC), for the first bit transmitted in
each time slot. The offset is the number of data periods by which
transmission of the first bit on [C] is delayed. All subsequent
transmissions of the first bit follow this offset. One data period (1 bit)
equals 4 cycles of CK8M for CMS = 1, and 2 cycles of CK8M for
CMS = 0.
C transmit clock edge.
0 = transmit on falling edge of CK8M*.
1 = transmit on rising edge of CK8M*.
0x2E
CULAW
0x2E
CUAADJ
0x2E
CPY[2:0]
0x2F
CXBOFF[3:0]
0x2F
CXCE
0x2F
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