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參數(shù)資料
| 型號(hào)： | STLC5460 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Line Card Interface Controller(線路卡片接口控制器) |
| 中文描述： | 線卡接口控制器（線路卡片接口控制器） |
| 文件頁數(shù)： | 28/54頁 |
| 文件大?。?/td> | 376K |
| 代理商： | STLC5460 |
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EXTRACTION A REGISTER(EXT A)
7
0
EA7
EA6
EA5
EA4
After Reset 00 (H)
EA3
EA2
EA1
EA0
EA 0/7
This register containsthe data extractedduring the Time Slot of Input multiplex
indicatedby the Command Memory. After loading, EXT interrupt is generated,in
accordancewith NEWE bit of Comparison Register
EXTRACTION B REGISTER(EXT B)
7
0
EB7
EB6
EB5
EB4
After Reset 00 (H)
EB3
EB2
EB1
EB0
EB 0/7
This register containsthe data extractedduring the Time Slot of Input multiplex
indicatedby the Command Memory. After loading, EXT interrupt is generatedin
accordancewith NEWE bit of ComparisonRegister.
INTERRUPT REGISTER (INT)
7
0
LSYNC
PDIF
PRS
MONR
After Reset 00 (H)
MONT
CIR
EXT
INS
LSYNC
Lost synchronisation.
LSYNC= 0, PFSsignal frequencyis correct.
LSYN = 1. PFSsignal has not occurredwhen expected,
or if Double clock the numberof clockpulses received is odd,
or the data rate of one PCM received is not Modulo4 bits at 8 Mb/s,
or the data rate of one PCM received is not Modulo2 bits at 4 Mb/s.
PCM different.
PDIF = 1. If one (or more)comparison (validated by the Comparison Register)
between PCM is different.
PseudoRandomSequence .
Whenthe PRS analyser is validated(SAV=1), PRSbit is put to ”one” if the
synchronisation is performedor lost(see PRSR bit of StatusRegister).
Monitor ChannelReceive.
Whenthis bit is at ”1”, a byte has been received from the Monitor Channel defined by
Receive MonitorStatusRegister(or an event)
Monitor ChannelTransmit.
Whenthis bit is at ”1”, the MonitorChannel(defined by TransmitMonitor Status
Register)acknowledgesthe lastcommand required by the microprocessor.
Command IndicateReceive.
Whenthis bit is at ”1”, a new primitive has been received from the Command/Indicate
channel definedby the Receive Command/IndicateStatus Register
Extract
Whenthis bit goes to ”1”, the Extract RegisterA or/andB can be read during 120
microsecondsbefore changing.
Insert
Whenthis bit goes to ”1”, the content of Insert Register A or/andB has been
transmitted.During 120 microsecondsbeforethe next transmission, the
microprocessor can write a newword in accordancewith TIM (Bit of CRRegister).
PDIF
PRS
MONR
MONT
CIR
EXT
INS
STLC5460
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