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參數(shù)資料
| 型號： | STLC5460 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Line Card Interface Controller(線路卡片接口控制器) |
| 中文描述： | 線卡接口控制器（線路卡片接口控制器） |
| 文件頁數(shù)： | 19/54頁 |
| 文件大?。?/td> | 376K |
| 代理商： | STLC5460 |
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IM0
IncomingMultiplex 0 Assignment.
IM0
0
1
Incoming Multiplex0 receives data from
Pin DIN 0 (DefaultValue)
Pin DIN 1
OUTPUT MULTIPLEX ASSIGNMENT REGISTER (OMASS)
7
-
0
-
-
-
0
DO1
0
DO0
After Reset 04 (H)
DO1
Output 1 Pin Assignment.
DO1
0
1
DOUT 1 pin receives datafrom
OutgoingMultiplex 0
OutgoingMultiplex 1 (Default value)
DO0
Output 0 Pin Assignment.
DO1
0
1
DOUT 0 pin receives datafrom
OutgoingMultiplex 0 (Default value)
OutgoingMultiplex 1
WORKINGREGISTERDESCRIPTION
Command Register(CMR)
7
0
R/W
CM
CR5
CR4
After Reset 00 (H)
CR3
CR2
CR1
CR0
R/W
Read/Write
R/W = 0. Writememory.
Address bits are provided by the DestinationRegister (DST)
Data bits are provided by the Source Register (SRC)
R/W = 1. Read Memory.
Address bits are provided by the Destination Register (DST)
Data bits will be in Source Register (SRC) when BUSY (Status Register) will go to ”0”.
CM
Command memory.
CM = 1 Accessto Command Memory
CM = 0 Accessto Auxiliary Memory.
CR 5/0
The meaning of these bits depends on the value of CM and R/W. The description is
given thereafter.
CM = 1
Command Memory
CM = 0
Auxiliary Memory
Command RegisterBit 5 to 0
Subchannelconfiguration
Command if Write Memory
Statusif Read Memory
Byte if MONchannel or Primitive
if C/I channel.
1 of 16 MONchannels
or 1 of 16 C/I channels
SourceRegister
1 of 192 Input Time Slots or 1 of
2 InsertionRegisters
1 of 192 OutputTime Slots or 1
of 2 ExtractionRegisters
DestinationRegister
Following you will find a detailed explanationcase by case of the meaningof all the bits of this register.
STLC5460
19/54
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