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參數(shù)資料
| 型號： | STLC5460 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Line Card Interface Controller(線路卡片接口控制器) |
| 中文描述： | 線卡接口控制器（線路卡片接口控制器） |
| 文件頁數(shù)： | 2/54頁 |
| 文件大?。?/td> | 376K |
| 代理商： | STLC5460 |
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DESCRIPTION
The Line Card Interface Controller, STLC5460, is
a monolithic switching device for the path control
of up to 128 channels of 16, 32, 64 kbps band-
width. Two consecutive 64 kbps channels may
also be handled as a quasi single 128 kbps chan-
nel. For these channels, the LCIC performs non-
blocking space time switching between two serial
interfaces: the system interface (or PCM inter-
face)and the generalcomponentinterface (GCI).
PCM interface can be programmed to operate at
different data rates between 2048 and 8192 kbps.
The PCM interface consists of up to four duplex
ports with a tristate indication signal for each out-
put line. The GCI interface can be selected to be
PCM interface at 2Mbit/s.
The LCIC can be programmed to communicate
with GCI compatible devices such as STLC3040
(SLIC), STLC5411 (U interface) and others. The
device manages the layer 1 protocol buffering the
Command/Indicateand Monitor channels for GCI
compatible devices.
Due to its capability to switch channelsof different
bandwidths, the STLC5460 can handle up to 16
ISDN subscribers with their 2B+D channel struc-
ture in GCI configuration, or up to 16 analog sub-
scribers. Since its interfaces can operate at differ-
ent data rates, the LCIC is an ideal device for
data rate adaptationbetween PCM interface up to
8Mb/s and GCI at 2Mb/s.
The device gives the possibility of checking the
correct communication inside the PBX or Public
CentralOffice providing:
- independentPCM delay setting
- PCM comparison function
-PseudoRandomSequenceGeneratorandAnalyser.
Moreover, the LCIC is one of the key building
blocks for networks with either central, distributed
or mixed signaling and packet data handling ar-
chitectures associated with ST5451 (HDLC con-
troller).
The device is controlledby a standard8 bit paral-
lel microprocessor interface with a multiplexed
address-data bus. The device may optionally be
controlledby separate address and data buses.
DESTINATION REG
COMMAND REG
SOURCE REGISTER
COMMAND MEMORY
194 WORDS OF 14 BITS
COUNTERS
PARALLEL
SERIAL
SHIFTING
4 PCM
2 GCI
C/I, MON
TRANSMIT
16
INDIPENDENT
CONTROLLERS
SPECIAL
SWITCH
AT
16, 32, 64
KB/S
EXTRACTION
2 x 64
Kbit
CHANNEL
(ADDRESS)
(DATA)
(DATA)
SWITCHING
MEMORY
194
BYTES
(4PCM+2GCI + 2
CHANNEL -INSERTION- =
128+64+2=194)
COUNTERS
C/I, MON
RECEIVER
INSERTION
2 x 64
Kbit
CHANNEL
SERIAL
PARALLEL
SHIFTING
4 PCM
2 GCI
1 bit for 16 tristate
6 bits
D94TL160A
BLOCK DIAGRAM
STLC5460
2/54
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參數(shù)描述 |
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| STLC5460FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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| STLC5465B | 功能描述:電信集成電路 Multi-HDLC Sw Matrix RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
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