參數(shù)資料
型號(hào)： STLC5460
廠商： 意法半導(dǎo)體
英文描述： Line Card Interface Controller(線路卡片接口控制器)
中文描述： 線卡接口控制器（線路卡片接口控制器）
文件頁(yè)數(shù)： 24/54頁(yè)
文件大小： 376K
代理商： STLC5460
N0 = 1
TS0/4
N1 = 1
N0 = 0 and TS0/4 = 0. A InsertionRegister40 (H) is the source
N0 = 1 and TS0/4 = 1. B InsertionRegister41(H) is the source .
Multiplexnumber : 1
Time Slot Number: 0 to 31
Insertion Registers are selected.
If
Second case : CM = 0 (Bitof Command Register)
The auxiliary memory is selected.
If channel is Monitorchannel (seeDestination Register), the contentsof Source Register aredata :
SR7
M8
SR6
M7
SR5
M6
SR4
M5
SR3
M4
SR2
M3
SR1
M2
SR0
M1
It is proposedto initialiseat FF, beforestartingnormal operation using initialisation register
T1 = 0 and T0 = 1.
M8 will be transmittedfirst.
If channel selected by DestinationRegister is Command/Indicatechannels, the mean of bits of Source
Register are :
- For TX C/I with R/W = 0 Writeauxiliary memory.
SR7
-
SR6
-
SR5
C6
SR4
C5
SR3
C4
SR2
C3
SR1
C2
SR0
C1
It is proposedto initialiseat FF, beforestartingnormal operation using initialisation register
T1 = 0 and T0 = 1.
C1/C6
Primitive to transmit: C6 and C5 bits are taken into accountdepending
on CI4M1 and CI4M0bits of MCONFRegister.C6 (or C4) will be
transmittedfirst.
- For TX C/I with R/W = 1 Read auxiliary memory.
SR7
PT1
SR6
PT0
SR5
C6
SR4
C5
SR3
C4
SR2
C3
SR1
C2
SR0
C1
PT 1/0
Statusof Transmitting primitive.
PT1
0
PT0
0
Status
Primitive has not been transmittedyet
Primitive has been transmitted once
Primitive has been transmitted twice
Primitive has been transmitted more than twice.
0
1
1
0
1
1
C6 to C1
For RX C/I with R/W = 0, write auxiliarymemory. This SourceRegister is not takeninto account.
For RX C/I with R/W = 1, read auxiliary memory.
Primitive being transmitted.
SR7
OVR
SR6
PR
SR5
C6
SR4
C5
SR3
C4
SR2
C3
SR1
C2
SR0
C1
STLC5460
24/54
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