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參數(shù)資料
| 型號(hào)： | STLC5460 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Line Card Interface Controller(線路卡片接口控制器) |
| 中文描述： | 線卡接口控制器（線路卡片接口控制器） |
| 文件頁數(shù)： | 21/54頁 |
| 文件大?。?/td> | 376K |
| 代理商： | STLC5460 |
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SECONDCASE CM = 0: ACCESSTO AUXILIARYMEMORY
Microprocessor writes Auxiliary Memory to transmit Primitives for each TX C/I channel and to transmit
Bytes of messagefor each TX MONchannel.
Microprocessor reads Auxiliary memory to recover Primitive received by each RX C/I channel and to re-
cover the message received by each RX MON channel.
TX Command Indicate channel - Selectedby Destination Register(DST)
CM
0
CR5
-
CR4
-
CR3
-
CR2
-
CR1
PT1
CR0
PT0
R/W
R/W = 1
Read auxiliarymemory
After writing this register with R/W=1 and when BUSY(statusregister)has gone to 0, the
bits of the registerhave the following meaning:
CR5/CR2
Not used
PT0/1
Primitivetrasmitted
PT1
0
PT0
0
Status
Primitive has not been transmittedyet
Primitive has been transmitted once
Primitive has been transmitted twice
Primitive has been transmitted more than twice.
0
1
1
1
0
1
R/W = 0
Write auxiliary memory.
CR0/CR5
not used
RX CommandIndicate channel - Selectedby Destination Register (DST)
CM
0
CR5
-
CR4
-
CR3
-
CR2
-
CR1
OVR
CR0
PR
R/W
R/W = 1
Read auxiliarymemory
After writing this register with R/W=1 and when BUSY(status register) has gone to 0, the bits of the
registerhave the following meaning:
CR5/CR2
Not used
OVR
Overrun
OVR = 1. The previous primitive has not been read by the microprocessor.
PR
PrimitiveReceived.
PR = 1. The primitivehas been receivedonce
PR = 0. The primitivehas been receivedtwice or more.
The primitive is in Source Register.
R/W = 0
Writing auxiliary memory.
CR0/CR5
not used
STLC5460
21/54
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