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參數(shù)資料
| 型號： | STLC5460 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Line Card Interface Controller(線路卡片接口控制器) |
| 中文描述： | 線卡接口控制器（線路卡片接口控制器） |
| 文件頁數(shù)： | 27/54頁 |
| 文件大?。?/td> | 376K |
| 代理商： | STLC5460 |
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BUSY
Busy.
The memories cannot be accessedif thisbit is at ”1”. In this case, a newaccess of
three memory access registers[Command Register(CMD); source Register (SRC)
and DestinationRegister (DST)]will be ignored. If the microprocessorhas Twait
cycles(working with DTACKor READY),the test BUSY is not necessary.
PseudoRandomSequence Recovered.
Whenthe PRS analyser is validated,PRS bit is put to ”one” if the synchronizationis
performed.
Monitor ChannelReceive.
Whenthis bit is at ”1”, a byte has been received from one or moreMonitor channel.
The microprocessor must read the Receive Monitor StatusRegister (RMS)
Monitor ChannelTransmit.
Whenthis bit is at ”1”, one (or more) channel is transmitting a message and is
ready to transmita new byte of this message.The microprocessor must read the
Transmit MonitorStatus Register(TMS).
Whenthis bit is at ”0”, each channelis IDLE, and is ready to transmit a new message.
Command/IndicateReceive.
Whenthis bit is at ”1”, a new primitive has been received from one or more
Command/Indicatechannel.The microprocessorcan read the Receive
Command/IndicateStatusRegister (RCIS).
Extract Status.
This bit is put ot ”1” when a new bytehas been written in theextract registersA or/
and B, when it is at ”1” the Extract Registerscan be read during120 microseconds
before changing.The bit is reset after the readingof theSTATUS Register.
Insert Status.
Whenthis bit is at ”0”, the Insert RegisterA or/andB can be written during 120
μ
s
before the next transmission. After the InsertRegisters havebeen writtenthe bit goes
automaticallyto ”1”, the bit is put at ”0” after the reading of the statusregister.
PRSR
MONR
MONT
CIR
EXT
INS
INSERTION A REGISTER(INS A)
7
0
IA7
IA6
IA5
IA4
IA3
IA2
IA1
IA0
After Reset 00 (H)
IA 0/7
This register containsthe data to insert during the Time Slot (s) of the output
multiplex(es) indicated by the Command Memory. After transferring INS, interruptis
generated
INSERTION B REGISTER(INS B)
7
0
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
After Reset 00 (H)
IB 0/7
This register containsthe data to insert during the Time Slot(s) of the output
multiplex(es) indicated by the Command Memory. After transferring,INS interruptis
generated.
STLC5460
27/54
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