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參數(shù)資料
| 型號(hào)： | STLC5460 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Line Card Interface Controller(線路卡片接口控制器) |
| 中文描述： | 線卡接口控制器（線路卡片接口控制器） |
| 文件頁數(shù)： | 9/54頁 |
| 文件大小： | 376K |
| 代理商： | STLC5460 |
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MEMORY STRUCTURE AND SWITCHING
The LCIC contains three memories: Auxiliary
Memory (AM), Data Memory (DM) and Control
Memory (CM).
The Auxiliary Memory consists of one block di-
vided in four parts of 16 words.
This Auxiliary Memory is used for validated data
from Monitor and Command/IndicateRx channels
and
to transmit data to Monitor and Com-
mand/IndicateTx channels.
The Data Memory buffers the data input from the
PCM and the GCI interface. It has a capacity of
128 + 64 time slots to buffer 4 PCM frame of 32
time slots and two GCI interfaces. It is written pe-
riodically once every 125 microseconds controlled
by the input counters associated to PCM interface
and to GCI interface. To perform the switchingthe
loopback function, this memory is read, random,
in accordancewith the control memory
The Control Memory has a capacity of 128 + 64
words of 14 bits: 8 of data and 6 of code. The 14
bits are written random, via microprocessor in-
terface and read cyclically under the control of
the output counters associated to PCM interface
and GCIinterface.
For
control memory access and different func-
tions, three registersare provided:
destination register:
it contains the address of a specific location of
the control memory;
source register :
it contains the data (to be written or read) of the
control memory corrisponding to the address indi-
catedby thedestinationregister;
commandregister:
it contains the code (6 bits to be written or read)
of the control memory.
The content of command register defines the dif-
ferent capabilities: switching at 64 kb/s, 32 kb/s,
16 kb/s, loopback and also extraction/insertion
from the microprocessor interface.
A memory access using the actual command reg-
ister and source register is performed upon every
destination register write access. The processing
of the memory accesstakes at most488ns.
MICROPROCESSOR INTERFACE
After Reset, the Microprocessor interface is in
non-multiplexed mode (Address bus and Data
bus must be non-multiplexed):
if ALE pin is hardwired at VSS, the Microproces-
sor interface is Motorola like, Address/Data are
non-multiplexed.
if ALE pin is hardwired at VDD the Microproces-
sor interface is Intel like, Address/Data are non-
multiplexed.
After Reset, as soon as two successiveedges are
detected on ALE pin (Rising and falling edges) by
the circuit the Microprocessor interface switches
in multiplexed mode (Address bus and Data bus
must be multiplexed). The circuit is set automat-
ically in Motorolalike or inIntel like mode.
For the circuit Address bus and Data bus multi-
plexed or not multiplexed, the difference between
Motorolalikeand Intellikemodeis showedin fig. 4.
Figure 4.
STLC5460
9/54
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