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參數(shù)資料
| 型號(hào)： | STLC5460 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Line Card Interface Controller(線路卡片接口控制器) |
| 中文描述： | 線卡接口控制器（線路卡片接口控制器） |
| 文件頁(yè)數(shù)： | 41/54頁(yè) |
| 文件大?。?/td> | 376K |
| 代理商： | STLC5460 |
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AUXILIARYMEMORY ACCESSES:CM=0
Write
Auxiliary Memory:
Receive command / indicate
channels
CMD and SRC registersare writtenif theirbits have not the rightvalue.
CMD and SRC registerscan be written in any order.
DST registeris always written the last.
R CM
0
Bits not used
0
Primitiveto initiate
CMD
SRC
DST
4 or 6
6
I
&
N
AUXILIARYMEMORY
16 wordsassigned to
8 RX C/I channels of MUX0
8 RX C/I channels of MUX1
A
R=0 Write
CM=0 Auxiliary Memory
MONTX 1 of 16 TX C/I
0
0
channels
Read
AuxiliaryMemory in two steps:
Receive command/ indicate
channels
Firststep: register writing:
CMD register is writtenif its bits are not the right value.
SRC registeris not written.
DST registeris alwayswritten the last.
R CM
1
bits not used
0
Register not written
CMD
SRC
DST
R CM
1
channel status
0
channel status & Primitive
which has been received
MON TX
0
1 of 16 TX C/I
channels
0
CMD
SRC
DST
6
4 or 6
2
A
2
AUXILIARYMEMORY
16 words assigned to
8 RX C/I channels of MUX0
&
8 RX C/I channels of MUX1
OUT
OUT
MON TX
0
1 of 16 TX C/I
channels
0
Secondstep: register reading:
CMD and SRC registers may be read in any order.
DST registeris not changed.
STLC5460
41/54
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