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參數(shù)資料
| 型號(hào)： | STLC5460 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Line Card Interface Controller(線路卡片接口控制器) |
| 中文描述： | 線卡接口控制器（線路卡片接口控制器） |
| 文件頁數(shù)： | 12/54頁 |
| 文件大?。?/td> | 376K |
| 代理商： | STLC5460 |
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CONFIGURATION REGISTER DESCRIPTION
Initialisationand Identification Register (IIR)
7
0
RBS
RST
T1
T0
V3
V2
V1
V0
After Reset 3F (H)
T1/T0 Testfunctions
T1
0
0
T0
0
1
Description
Normal State
Command Memory or Auxiliary Auto Reset.
If CM = 1 (Bit of Command Register):
the six lower bits of command Register and the eight bits of Source Register are stored
into each address of command Memory.
If CM = 0 (Bit of Command Register) :
the eight bits of Source Register are stored into each address of Monitor Auxililary
Memory and the six lower bits of Source Register are stored intoCommand/Indicate
Auxilliary Memory.
The 16 C/I and Monitor channels are ready to transmitand to receive data.After
AutoReset, BUSY and T0 goes to ”0”.
Auto Test. This function is reserved for manufacturer.
- The Pseudo Random Sequence generator is connected instead of Insert A Register and
Pseudo Random Sequence Analyzer is connected instead of Extract A Register.
- The Command Memory is loaded thanks to a specialalgorithm in order to switch the
sequence provided by the generator into TSO of PCMO, then the contents of TSO of
PCMO into TS1 of PCMO, then the contents of TS1 of PCMO into TS2 of PCMO and
so on.
Finally, the contentsof TS31 of MUX1 aretaken into account by the Pseudo Random
Sequence Analyzer.After loading Command Memory, 193 switching are set up in real
time.The analyzer receives the Pseudo Random Sequence from the generator after
switching.
If LP = 1, the loopback is internal.
If LP = 0, an external loopback must be performed. So, Command Memoryand Data
Memory can bechecked in the same time.
Reserved. Initialise CM so that the content of each input Time Slot t of input multiplex m is
switched to output Time Slot t of output multiplex m
1
1
1
1
RBS
Register Bank Selection.
RBS = 0. The 16 first main registersare selected(0 to 15).
RST
Reset Soft.
the programmableregisters are reset.
V3/V0
these bits are fixed at 0
COMPARISONREGISTER (COMP)
7
0
NEWE
TIM
CP6
CP5
After Reset 00 (H)
CP4
CP3
CP2
CP1
NEWE
New EXTRACT.
When NEWE = 1, EXT interrupt is generated only if a new word is loaded into
EXTRACT Registers(A or B).
TIM
Timer, associatedto INS of INT Registerand to TIMO/1 of CPOFregister.
TIM = 1
TIM0/1bits of CPOFregister are taken into account
TIM = 0
an interruptis generatedeach 125
μ
s.
STLC5460
12/54
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