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參數(shù)資料
| 型號： | STLC5460 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Line Card Interface Controller(線路卡片接口控制器) |
| 中文描述： | 線卡接口控制器（線路卡片接口控制器） |
| 文件頁數(shù)： | 26/54頁 |
| 文件大?。?/td> | 376K |
| 代理商： | STLC5460 |
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Second Case CM = 0 (Bit of CommandRegister).
The auxiliary Memory is selected.
PCM
-
DT6
MON
DT5
TX
DT4
-
DT3
M0
DT2
G2
DT1
G1
DT0
G0
PCM Bit is not significant.The other bitsare relevant onlyif multiplexis GCI (See bits of Multiplex Con-
figurationRegister : GCI M0 and/or GCI M1).
MON
Command/Indicate
MON= 0. The channelis Command/Indicate
MON = 1. Thechannel is MON channel.
TX
Transmitter
TX = 1. The transmit channel is selected.
TX = 0. The receive channel is selected.
M0
Multiplex 0.
M0 = 0. The GCI multiplex 0 is selected.
M0 = 1. The GCI multiplex 1 is selected.
G2/G0
GCI 0/2
One of eightGCI channelsof the multiplex selected(one GCI channel is
constituted by five sub-channels: B1, B2, D, C/I and MON).
If Multiplexis not GCI,the GCI channelsare not validated.The 32 Time Slots of the multiplex can be
used forswitching.
STATUS REGISTER(STATUS)
7
0
BID
BUSY
PRSR
MONR
After Reset 00 (H)
MONT
CIR
EXT
INS
Each bit of this register is read only, except BID (bit) whichcan be writtenand read by the microproces-
sor.
BID
Bi-directionalSwitching.
BID = 1. two connection paths are establishedwith the same
μ
p instruction.
The
μ
p writes successivelyinto three register: Command Register, SourceRegister
and the Destinationregister lastly, when the Destinationregisterhas been written a
write command memory startsto set up the connectionrequired by the
μ
p.
The same informationis usedto establish a symmetrical connection:
Source register and Destinationregisterare swapped,and so are the SS0/1and
DS0/1bit of Command Register.
BID = 0: one connectionpath is established.
The
μ
p writes successivelyinto three register: Command register, Source register
and Destinationregister lastly, when the Destinationregister has been written a write
commandmemory start to set up the connectionrequired by the
μ
p.
STLC5460
26/54
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