參數(shù)資料
型號(hào)： STLC5460
廠商： 意法半導(dǎo)體
英文描述： Line Card Interface Controller(線路卡片接口控制器)
中文描述： 線卡接口控制器（線路卡片接口控制器）
文件頁(yè)數(shù)： 20/54頁(yè)
文件大?。?/td> 376K
代理商： STLC5460
FIRST CASE CM = 1: ACCESS TO COMMAND MEMORY
CM
1
CR5
CH1
CR4
CH0
After Reset 00 (H)
CR3
SS1
CR2
SS0
CR1
DS1
CR0
DS0
R/W
R/W
Read/Write
R/W = 0 (Write). The eight bits of Source Register and the six lower bits of this
Command Register are loaded into the Command Memory (14 bits). The Address bits
are given by the Destination Register (8 bits). Write cycle starts when Destination
Register is loaded by the microprocessor.
R/W = 1 (Read).
The 14 bits of Command memory addressed by the Destination Register are loaded
respectively into Command Register (6 bits) and Source Register (8 bits). Read cycle
starts whenDestinationRegisteris loaded by the micro-processor.
CH0/1
Channel Data Rate
CH1
0
0
CH0
0
1
Description
The output is at high impedance during the time slot selected
16kb/ssubchannelis selected
32kb/ssubchannelis selected
64kb/schannel is selected
1
0
1
1
During the time slot selected,the output is at high impedancefor the subchannelsnot selected.
SS 0/1
SourceSubchannelselected.
Data Rate
SS1
0
0
1
1
0
0
SS0
0
1
0
1
0
1
Source channel
Bits 6-7
Bits 4-5
Bits 2-3
Bits 0-1
Bits 4 to 5
Bits 0 to 3
16kb/s
32kb/s
Bit 7 is trasmittedfirst.
DS 0/1
DestinationSubchannelselected.
Data Rate
SS1
0
0
1
1
0
0
SS0
0
1
0
1
0
1
Source channel
Bits 6-7
Bits 4-5
Bits 2-3
Bits 0-1
Bits 4 to 5
Bits 0 to 3
16kb/s
32kb/s
Bit 7 is trasmittedfirst.
STLC5460
20/54
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