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參數(shù)資料
| 型號： | STLC1502 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | VOICE OVER IP PROCESSOR |
| 中文描述： | IP語音處理器 |
| 文件頁數(shù)： | 68/81頁 |
| 文件大小： | 526K |
| 代理商： | STLC1502 |
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STLC1502
68/81
Figure 14: PCM-block Interconnection Scheme
The PCM interface has 5 main signals:
DR (output): this is the serial data stream that the PCM sends to the codec
DX (input): this is the serial data stream sent by the codec and received by the PCM block
PCLK (input/output): this is the PCM clock sent to codec. In the application, the frequency is
2.048Mhz. The PCM clock can be generated by the PCM block from internal Master clock or can be
input externally, according to the bit CLKEN in configuration register
PFS (input/output): this signal is asserted high when the frame number zero is present on the serial
data stream; it is possible to program the codec so that the PCM block asserts this signal on a given
frame (FS). The same frame number is always present in the same time on DR and DX. The PFS
can be generated by division from PCLK or can be input externally, according to FSEN in the config-
uration register.
10.1 Miscellaneous Interface
This interface has two signals:
RSTn (input): this is the hardware active low reset
CLK (input): this is the master input clock coming from the external oscillator at 2.048Mhz in the cur-
rent application.
10.2 Interrupt Event Management
There are two interrupt lines that goes to the D950.
ITR3 line (Overrun)
ITR7 line (Frame synch).
DR
DX
PCLK
PFS
P
XAE(15:0)
XDE(15:0)
XWREn
XRDEn
XBSEn
ITR3n
ITR7n
RSTn
CLK
D
M
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