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參數(shù)資料
| 型號： | STLC1502 |
| 廠商： | 意法半導體 |
| 英文描述： | VOICE OVER IP PROCESSOR |
| 中文描述： | IP語音處理器 |
| 文件頁數(shù)： | 40/81頁 |
| 文件大?。?/td> | 526K |
| 代理商： | STLC1502 |
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STLC1502
40/81
Int.Base + 0x0C
IRQSoft
R/W
Only the bit 1 has to be used.
Writing ‘1’ it generates an inter-
rupt mapped in the bit 1 of the
IRQStatus and of the IRQRaw-
Status registers. Writing ‘0’ the
software interrupt cause is
erased.
Int.Base + 0x10
FIQStatus
R
For the FIQ interrupt cause, ‘1’
means an active pending inter-
rupt that has to be served by
the ARM.
Int Base + 0x14
FIQRawStatus
R
For the IRQ interrupt source, a
‘1’ means an active pending
interrupt “before” the mask (w/
o considering the mask)
Int.Base + 0x18
FIQEnableSet
R/W
For the FIQ interrupt source, a
‘0’ means that even if an inter-
rupt source is active, it has to
be stopped (masked). The
write operation of 1 to the bit0,
enables the interrupt
Int.Base + 0x1C
IRQEnableClear
W
The write operation of 1 to a
given bit, disables the corre-
sponding interrupt. As conse-
quence, the corresponding bit
in the IRQEnableSet goes to 0
(interrupt disabled).
Int.Base + 0x20
FIQEnableClear
W
The write operation of 1 into
the bit 0 disables FIQ interrupt
cause. As a result, the bit 0 in
the FIQEnableSet goes to 0
(interrupt disabled).
Int.Base + 0x24
IRQTestSource
R/W
Usable when the bit 0 of the
IRQSourceSel is set to one. In
this case this register is the
interrupt source cause. If set,
the cause is active (interrupt
generated) while if reset, the
cause is not active.
Address
Register Name
R/W
Notes
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| STLC1502D | 制造商:STMicroelectronics 功能描述:VOIP STRADIVARIUS 1 - Trays |
| STLC1502P | 制造商:STMicroelectronics 功能描述:VOICE OVER IP PROCESSOR - Trays |
| STLC1510 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NorthenLite G.lite DMT Transceiver |
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| STLC1512 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NorthenLite⑩ G.lite BiCMOS Analog Front-End Circuit |
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