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參數(shù)資料
| 型號(hào)： | STLC1502 |
| 廠(chǎng)商： | 意法半導(dǎo)體 |
| 英文描述： | VOICE OVER IP PROCESSOR |
| 中文描述： | IP語(yǔ)音處理器 |
| 文件頁(yè)數(shù)： | 17/81頁(yè) |
| 文件大?。?/td> | 526K |
| 代理商： | STLC1502 |
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17/81
STLC1502
The EDM block includes a decoder in order to generate proper CS to the external device. In particular this de-
coder will work on bits 25 and 26 of internal ARM address bus.
EDM decoding scheme
Every CS space can be programmed through internal register in order to configure the EDM to work
with the proper external device
The DRAM Controller has nine registers, the configuration register, four bank registers and four
SDRAM configuration registers. The registers are accesses via the APB bus. The register data path
is 16 bits wide.
6.3.1 EDM Register Map [0x0C580000]
The base address of the EDM register is 0x0C580000
EDM_RAS
OUT
SDRAM RAS signal. Not used with EDO.
EDM_CAS
OUT
SDRAM CAS signal. Not used with EDO
OEN
OUT
SRAM Output Enable. Not used with
SDRAM
EDM_WE
OUT
DRAM Write Enable
EDM_BS(3:0)
OUT
SDRAM byte strobe. CAS when EDO memo-
ries are used
EDM_A(21::0)
OUT
DRAM address lines, only 14 lines are
driven.. Lines.21:14 are driven by static
memory controller
EDM_D(31:0)
INOUT
DRAM data lines, shared with static memory
controller lines.
EDM
Decoder
EDM_A(13:0)
Address
Register
Name
R/W
Notes
EDMBase +
0x00
MB1Config
R/W
Memory Bank 1 Configuration Register
EDMBase +
0x04
MB2Config
R/W
Memory Bank 2 Configuration Register
NAME
Signal type
Description
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