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參數(shù)資料
| 型號： | STLC1502 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | VOICE OVER IP PROCESSOR |
| 中文描述： | IP語音處理器 |
| 文件頁數(shù)： | 51/81頁 |
| 文件大?。?/td> | 526K |
| 代理商： | STLC1502 |
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STLC1502
to the rxfifo. If nothing happens, and the timeout counter reaches zero, the ASCStatus(Timeout-
NotEmpty) flag will be set. Provided ASCIntEnable(TimeoutNotEmpty) is set, this will cause an interrupt.
When the software has emptied the rxfifo, the timeout counter will reset and start decrementing. If no
more characters arrive, when the counter reaches zero the ASCStatus(TimeoutIdle) flag will be set. Pro-
vided the ASCIntEnable(TimeoutIdle) is set, per_interrupt will fire.
7.7.4 Interrupt control
The UART contains two registers that are used to control interrupts, the status register (ASCStatus) and
the interrupt enable register (ASCIntEnable). The status bits in the ASCStatus register determine the
cause of the interrupt. Interrupts will occur when a status bit is 1 (high) and the corresponding bit in the
ASCIntEnable register is 1.
The error interrupt signal is generated by the UART from the OR of the parity error, framing error, and
overrun error status bits after they have been ANDed with the corresponding enable bits in the ASCIn-
tEnable register. An overall interrupt request signal (per_interrupt) is generated from the OR of the Error
Interrupt signal and the TxEmpty, TxHalfEmpty, RxHalfFull, RxBufFull signals.
Note:
TxFull does not generate interrupt.
The status register cannot be written directly by software. The reset mechanism for the status register is
described below.
TxEmpty, TxHalfEmpty are reset when a character is written to the transmitter buffer.
TxFull is reset when a character is transmitted
RxBufFull and OverrunError are reset when a character is read from the receive Fifo.
The data error status bits (ParityError, FrameError) are reset when the character with error is read
from the receive Fifo.
7.7.5 UART Memory map
The base address of the UART interface is fixed by the APB bridge.
Address
Register Name
R/W
Notes
UART_regBase+ 0x00
ASCBaudRate
R/W
Baud rate generator register
UART_regBase+ 0x04
ASCTxBuffer
WO
Transmit buffer (Fifo)
UART_regBase+ 0x08
ASCRxBuffer
RO
Receive buffer (Fifo).
UART_regBase+ 0x0C
ASCControl
R/W
UART control register.
UART_regBase+ 0x10
ASCIntEnable
R/W
UART interrupt enable reg-
ister
UART_regBase+ 0x14
ASCStatus
RO
UART status register.
UART_regBase+ 0x18
ASCGuardtime
R/W
UART Guartime register.
UART_regBase+ 0x1C
ASCTimeout
R/W
UART Timeout register.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| STLC1502D | 制造商:STMicroelectronics 功能描述:VOIP STRADIVARIUS 1 - Trays |
| STLC1502P | 制造商:STMicroelectronics 功能描述:VOICE OVER IP PROCESSOR - Trays |
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| STLC1512 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NorthenLite⑩ G.lite BiCMOS Analog Front-End Circuit |
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