參數(shù)資料
型號(hào): STLC1502
廠商: 意法半導(dǎo)體
英文描述: VOICE OVER IP PROCESSOR
中文描述: IP語(yǔ)音處理器
文件頁(yè)數(shù): 4/81頁(yè)
文件大小: 526K
代理商: STLC1502
STLC1502
4/81
200 MHz
To change the D950 master clock frequency the following procedure must be followed:
1) Disable the D950 clock, by resetting the DCLK bit in the control register of the MISC Control register.
2) Wait 10 ARM cycles
3) Select a new D950 master clock, by writing the MISC Status register.
4) Wait 4 ms
5) Disable the D950 clock, by setting the DCLK bit in the MISC Control register.
An Internal divider provides an internal PCM clock, 2083 KHz, that is not exactly the standard 2048 KHz.
- An external PCM clock frequency can be applied using a dedicated crystal or oscillator, to provide exactly
8KHz synch and sampling clock on the PCM bus. (External pins configuration Testsel[3:0] at [0011]).
The PCM clock rate can be selected via software to achieve the following values:
1536 (24 Ch.) 2048 (32 Ch.) 4096 (64 Ch.) 8192 KHz (128 Ch.).
- The PCM clock and Frame synch signals can be selected as inputs or outputs, by programming the con-
trol register in the miscellaneous block.
4.0 Pin Descriptions
The STLC1502 will be delivered in:
PQFP 208 Pins
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