參數(shù)資料
型號: STLC1502
廠商: 意法半導(dǎo)體
英文描述: VOICE OVER IP PROCESSOR
中文描述: IP語音處理器
文件頁數(shù): 37/81頁
文件大?。?/td> 526K
代理商: STLC1502
37/81
STLC1502
Even if only a single bit position is defined for FIQ, the interrupt controller can drive one of the interrupt source
(IRQ interrupt sources), through a register, in order to generate the FIQ interrupt.
The IRQ interrupt controller uses a bit position for each different interrupt source.
All interrupt source inputs must be active HIGH and level sensitive and it remain active until the interrupt cause
has been cancelled.
No hardware priority scheme nor any form of interrupt vectoring is provided, because these functions can be
provided in software.
A programmed interrupt register is also provided to generate an interrupt under software control.
Every interrupt source can be masked.
7.4.1 Interrupt control
The IRQ interrupt management is done as described in the following:
An interrupt is generated by a given device/source;
This cause is readable by the IRQRawStatus register;
If not masked (the mask is set by IRQEnableSet and reset by IRQEnableClear), this interrupt will
generate a IRQ signal to the ARM and the interrupt source will be known by a read of the IRQStatus
register.
The ARM will serve the IRQ reading at first in the IRQStatus the active interrupt requests and will
execute with a given priority the proper interrupt routine. Every routine must erase (quite soon) in
some way its interrupt request source. This causes also for the proper bit in the IRQRawStatus regis-
ter and in the IRQStatus register to disappear.
The same interlock is present for the FIQ interrupt.
7.4.2 Interrupt control scheme
Timer2
UART
Dual Port RAM
I2C
Ethernet switch DMAC1
Ethernet switch DMAC2
SPI
DMAC
IRQ1/GPIO18
IRQ2/GPIO19
IKybd
HPI
Timer3
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