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參數(shù)資料
| 型號： | STLC1502 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | VOICE OVER IP PROCESSOR |
| 中文描述： | IP語音處理器 |
| 文件頁數(shù)： | 48/81頁 |
| 文件大小： | 526K |
| 代理商： | STLC1502 |
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STLC1502
48/81
Error Cases
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt if ITE is set.
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with
an interrupt if the ITE bit is set. To resume, set the START or STOP bit.
ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an
interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is
cleared).
Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possi-
ble 0 bits transmitted last. It is then necessary to release both lines by software.
Event Flags and interrupt generation diagram
7.6.4 I2C registers map [0X0C300000]
The base address of the Remap & Pause register is 0x0C300000.
The offset of any particular register from the base address is the following.
Address
Register
Name
R/W
Notes
I2C_regBase+ 0x20
I2CCR
R/W
I2C configuration register
I2C_regBase+ 0x24
I2CSR1
R/W
I2C status register 1
I2C_regBase+ 0x28
I2CSR2
R/W
I2C status register 2.
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| STLC1502D | 制造商:STMicroelectronics 功能描述:VOIP STRADIVARIUS 1 - Trays |
| STLC1502P | 制造商:STMicroelectronics 功能描述:VOICE OVER IP PROCESSOR - Trays |
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| STLC1512 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NorthenLite⑩ G.lite BiCMOS Analog Front-End Circuit |
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