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參數(shù)資料
| 型號： | STLC1502 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | VOICE OVER IP PROCESSOR |
| 中文描述： | IP語音處理器 |
| 文件頁數(shù)： | 44/81頁 |
| 文件大?。?/td> | 526K |
| 代理商： | STLC1502 |
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STLC1502
44/81
The offset of any particular register from the base address is the following.
7.6 I2C bus interface
The I2C Bus Interface serves as an interface between the microcontroller and the serial I2C bus. It pro-
vides both multimaster and slave functions, and controls all I2C bus-specific sequencing, protocol, arbi-
tration and timing. It supports fast I2C mode (400kHz).
7.6.1 Main Features
Parallel-bus/I2C protocol converter
Multi-master capability
7-bit/10-bit Addressing
Transmitter/Receiver flag
End-of-byte transmission flag
Transfer problem detection
I2C Master Features:
Clock generation
I2C bus busy flag
Arbitration Lost Flag
End of byte transmission flag
Transmitter/Receiver Flag
Start bit detection flag
Start and Stop generation
I2C Slave Features:
Stop bit detection
I2C bus busy flag
Detection of misplaced start or stop condition
Programmable I2C Address detection
Transfer problem detection
End-of-byte transmission flag
Transmitter/Receiver flag
7.6.2 General Description
In addition to receiving and transmitting data, this interface converts it from serial to parallel format and
vice versa, using either an interrupt or polled by software. The interface is connected to the I2C bus by a
data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus and a Fast
I2C bus. This selection is made by software.
The interface can operate in the following modes:
– Slave transmitter/receiver
– Master transmitter/receiver
Address
Register Name
R/W
Notes
SPI_regBase+ 0x04
SPIDR
R/W
SPI Data I/O register.
SPI_regBase+ 0x08
SPICR
R/W
SPI configuration register
SPI_regBase+ 0x0C
SPISR
R/W
SPI status register
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