參數(shù)資料
型號： STLC1502
廠商： 意法半導(dǎo)體
英文描述： VOICE OVER IP PROCESSOR
中文描述： IP語音處理器
文件頁數(shù)： 33/81頁
文件大小： 526K
代理商： STLC1502
33/81
STLC1502
Figure 10: Timer block diagram
The timer clock is generated by a prescale unit. The timer clock may be one of:
The CKTIMER
The CKTIMER divided by 16, generated by 4 bits of prescale
the CKTIMER divided by 256, generated by a total of 8 bits of prescale
Figure 11: Pre-scaler block diagram
Using the recommended 2.208Mhz clock, the minimum interval between two timer interrupt is 452nsec (corre-
sponding to the 2.208Mhz period) while the maximum interval between two timer interrupt is around 6sec.
7.1.3 Timer register map [0x0C000000]
The base address of the timer register is 0x0C000000
Terminal Count
Interrupt
Value
Load
Control
Timer
Clock
16-bit Down Counter
Load Register
Control Register
Divide
by 16
CKTIMER
Prescale
Select
Divide
by 16
Timer
Clock
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