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參數(shù)資料
| 型號： | STLC1502 |
| 廠商： | 意法半導體 |
| 英文描述： | VOICE OVER IP PROCESSOR |
| 中文描述： | IP語音處理器 |
| 文件頁數(shù)： | 13/81頁 |
| 文件大小： | 526K |
| 代理商： | STLC1502 |
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13/81
STLC1502
A scheme of the ESM control interface is reported in Figure 5.
Figure 5: ESM control interface
Every CS space can be programmed through internal register (one for each CS) in order to:
select the number of wait states to perform external access depending on the speed of the external
device mapped on that memory area
select if the data bus is x8 or x16 (available only for CS1 to CS2). When the x8 memories are used,
their data bus has to be placed on the ESM_D(7:0) signals
The wait states number for the external memories (depending on memory access time) is obtained from the
software code during the download phase. During the initialization phase, it is the responsibility of the software
to determine if a SRAM or a FLASH is present or not on a given CS space and the width of CS1-2 memories (if
WE[3:0]
OUT
Bytes Write enable. They are
used to select one/two bytes
when a x16/x32 Flash/SRAM is
present (shared with EDM).
0: lower byte
1: 2nd byte
2: 3rd byte
3: higher byte
ESM_CS0WIDTH
IN
This input informs whether a x8
(ESM_CS0WIDTH=0)
(ESM_CS0WIDTH=1) device is
present on the CS0. This informa-
tion is needed the boot from exter-
nal memory is selected.
or
x16
A[21:0]
OUT
22 Address lines for up to
4Mbytes address space (shared
with EDM A[13:0])
D[31:0]
INOUT
Data bus(shared with EDM bus)
NAME
Signal type
Description
ESM_CS(2:0)
OE
WE[3:0]
ESM_CS0WIDTH
external side
device side
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