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參數(shù)資料
| 型號(hào)： | STLC1502 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | VOICE OVER IP PROCESSOR |
| 中文描述： | IP語(yǔ)音處理器 |
| 文件頁(yè)數(shù)： | 49/81頁(yè) |
| 文件大小： | 526K |
| 代理商： | STLC1502 |
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STLC1502
7.7 UART-Universal Asynchronous Receiver Transmitter
The UART provides a serial data communication with transmit and receive channels that can operate
concurrently to handle a full-duplex operation. Two internal FIFOs for transmitted and received data,
deep 16 and wide 8 bits, are present; these FIFOs can be enabled or disabled through a register. Inter-
rupts are provided to control reception and transmission of serial data.
The clock for both transmit and receive channels is provided by an internal baud rate generator that
divides its input clock by any divisor value from 1 to 2 16 - 1.
7.7.1 Operation
The UART supports full-duplex asynchronous communication, where both the transmitter and the
receiver use the same data frame format and the same baud rate. Data is transmitted on the TXD pin and
received on the RXD pin.
Data frames
8-bit data frames either consist of:
eight data bits D0-7 (by setting the Mode bit field to 001);
seven data bits D0-6 plus an automatically generated parity bit (by setting the Mode bit field to 011).
Parity may be odd or even, depending on the ParityOdd bit in the ASCControl register. An even parity bit
will be set, if the modulo-2-sum of the seven data bits is 1. An odd parity bit will be cleared in this case.
The parity error flag (ParityError) will be set if a wrong parity bit is received. The parity bit itself will be
stored in bit 7 of the ASCRx-Buffer register.
8-bit data frame
9-bit data frames either consist of:
nine data bits D0-8 (by setting the Mode bit field to 100)
eight data bits D0-7 plus an automatically generated parity bit (by setting the Mode bit field to 111)
eight data bits D0-7 plus a wake-up bit (by setting the Mode bit field to 101)
I2C_regBase+ 0x2C
I2CCCR
R/W
I2C Clock Control register.
I2C_regBase+ 0x30
I2COAR1
R/W
I2C Own Address register
I2C_regBase+ 0x34
I2COAR2
R/W
I2C Own Address register
I2C_regBase+ 0x38
I2CDR
R/W
I2C Data I/O register.
Address
Register
Name
R/W
Notes
Start
bit
D0
(LSB)
D1
D2
D3
D4
D5
D6
1st
stop
bit
bit
8th
bit
stop
2nd
-Data bit (D7)
-Parity bit
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