
STLC1502
36/81
The base address of the WDT register is 0x0C500000
The memory map of the WDT peripheral is shown below:
7.3 Miscellaneous I/O
All the registers not related to any module attached to the APB/AHB bus such as EII, Test are considered Mis-
cellaneous I/O. Additionally, the ESM configuration register and the Dual Port register are also part of this block.
7.3.1 Miscellaneous Register Map [0x0C080000]
The Miscellaneous register address is
0x0C080000
7.4 Interrupt Controller
In an ARM system, two levels of interrupt are available:
FIQ (Fast Interrupt Request) for fast, low latency interrupt handling
IRQ (Interrupt Request) for more general interrupts
Ideally, in an ARM system, only a single FIQ source would be in use at any particular time. This provides a true
low-latency interrupt, because a single source ensures that the interrupt service routine may be executed direct-
ly without the need to determine the source of the interrupt. It also reduces the interrupt latency because the
extra banked registers, which are available for FIQ interrupts, may be used to maximum efficiency by preventing
the need for a context save.
Separate interrupt controllers are used for FIQ and IRQ.
There are 15 interrupt causes available in the IRQ controller coming from:
Software (internally generated)
Timer1
Address
Register Name
R/W
Notes
ESMBase + 0x00
WDTControl
R/W
WDT control register
ESMBase + 0x04
WDT reset_stat
R/W
WDT reset the status register
ESMBase + 0x08
WDT max_count
R/W
WDT programmable max count
ESMBase + 0x0C
WDT counter
R
WDT internal counter value
Address
Register Name
R/W
Notes
MISC_regBase+ 0x00
Control
W
This register allows to control the
reset/boot procedure and some
other control features
MISC_regBase+ 0x10
Status
W
This register allows DSP section
setting
MISC_regBase+ 0x20
IDENTIFICATION
R
This register provides informa-
tions about the device/system