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參數(shù)資料
| 型號： | SAA7115 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | PAL/NTSC/SECAM Video Decoder with Adaptive PAL/NTSC Comb Filter, High Performance Scaler, I2C Sliced Data Readback and SQ PIXEL OUTPUT |
| 中文描述： | PAL / NTSC制式/ SECAM視頻解碼器，自適應PAL / NTSC制式梳狀濾波器，高性能潔牙機，刨切的I2C數(shù)據(jù)回讀和SQ像素輸出 |
| 文件頁數(shù)： | 96/214頁 |
| 文件大?。?/td> | 732K |
| 代理商： | SAA7115 |
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Filename:
SAA7115_Datasheet.fm
Confidential - NDA required
page 96
Last edited by H. Lambers
Philips Semiconductors
CS-PD Hamburg
CVIP2
Datasheet
SAA7115
Date:
10/23/01
Version:
0.67
9.4.2
X-
PORT CONFIGURED AS INPUT
If data input mode is selected at the expansion port, then the scaler can choose its input data stream from the on-chip
video decoder, or from the expansion port (controlled by bit SCSRC[1:0] (91H[5:4]), C1H[5:4])). Byte serial Y-C
B
-C
R
4 : 2 : 2, or subsets for other sampling schemes, or raw samples from an external ADC may be input (see also bits
FSC[2:0] (91H[2:0], C1H[2:0])). The input stream must be accompanied by an external clock (XCLK), qualifier XDQ and
reference signals XRH and XRV. Instead of the reference signal, embedded SAV and EAV codes according to ITU 656
XRH and XRV carry the horizontal and vertical synchronization signals for the digital video stream through the expansion
port. The field ID of the input video stream is carried in the phase (edge) of XRV and state of XRH, or directly as FS
(frame sync, odd/even signal) on the XRV pin (controlled by XFDV (92H[7], C2H[7[), XFDH (92H[6], C2H[6]) and
XDV[1:0] (92H[5:4], C2H[5:4])).
The trigger events on XRH (rising/falling edge) and XRV (rising/falling/both edges) for the scalers acquisition window are
defined by XDV[1:0] and XDH (92H[2], C2H[2]). The signal polarity of the qualifier can also be defined (bit XDQ (92H[1],
C2H[1])). Alternatively to a qualifier, the input clock can be applied to a gated clock (means clock gated with a data
qualifier, controlled by bit XCKS (92H[0], C2H[0])). In this case, all input data will be qualified.
In case if 16 bit wide data input is required for the X-port input then the HPD[7:0] port is enabled for input via SCSRC[1:0]
(91H[5:4], C1H[5:4]) whilst the I-port must be set to 8-bit output mode by ICKS[3:0] (80H[3:0]).
9.5
Image port (I-port)
The image port transfers data from the scaler as well as from the VBI-data slicer, if selected (maximum 33 MHz). The
reference clock is available at the ICLK pin, as an output, or as an input (maximum 33 MHz). As output, ICLK is derived
either from the line-locked decoder or from the expansion port input clock or from PLL2/CGC2 combination, which
enables square pixel clock generation feature.
The data stream from the scaler output is usually discontinuous, which basically depends on the scale ratio. Therefore
valid data during a clock cycle is accompanied by a data qualifying (data valid) flag on pin IDQ. For pin constrained
applications the IDQ pin can be programmed to function as a gated clock output (bit ICKS2[80H[2]]).
The pulsegenerator allows however to squeeze all pixels of a video line so that a continuous video stream at the I-port
output is obtained. For details refer to chapter 8.2..
The data formats at the image port are defined in Dwords of 32 bits (4 bytes), such as the related FIFO structures.
However the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to HPD0
are used for chrominance data. The four bytes of the Dwords are serialized in words or bytes.
Available formats are as follows:
Y-C
B
-C
R
4 : 2 : 2
Y-C
B
-C
R
4 : 1 : 1
Raw samples
Decoded VBI-data.
For handshake with the receiving VGA controller, or other memory or bus interface circuitry, F, H and V reference signals
and programmable FIFO flags are provided. The information is provided on pins IGP0, IGP1, IGPH and IGPV. The
functionality on these pins is controlled via subaddresses 84H and 85H.
VBI-data is collected over an entire line in its own FIFO, and transferred as an uninterrupted block of bytes. Decoded
VBI-data can be indicated by the VBI flag on pin IGP0 or IGP1.
As scaled video data and decoded VBI-data may come from different and asynchronous sources, an arbitration scheme
is needed. Normally the VBI-data slicer has priority.
The image port consists of the pins and/or signals, as listed in Table 40.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7115AHL/V1 | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115AHL/V1,518 | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115AHL/V1,557 | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115AHL/V1-T | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115HL/V1 | 制造商:NXP Semiconductors 功能描述:IC VIDEO DECODR DIGITAL 100 |
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