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Filename:
SAA7115_Datasheet.fm
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page 61
Last edited by H. Lambers
Philips Semiconductors
CS-PD Hamburg
CVIP2
Datasheet
SAA7115
Date:
10/23/01
Version:
0.67
8.3.3.2
Vertical scaler (subaddresses B0H to BFH and E0H to EFH)
Vertical scaling of any ratio from 64 (theoretical zoom) to
1
63
(icon) can be applied.
The vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different
modes; Linear Phase Interpolation (LPI) and accumulation (ACM) mode. These are controlled by YMODE[B4H[0]]:
LPI mode
: In LPI mode (YMODE = 0) two neighbouring lines of the source video stream are added together, but
consecutive input lines only. LPI mode should be applied for scaling ratios around 1 (down to
1
2
),
it must be applied
for vertical zooming
.
ACM mode
: The vertical Accumulation (ACM) mode (YMODE = 1) represents a vertical averaging window over
multiple lines, sliding over the field. This mode also generates phase correct output lines. The averaging window length
corresponds to the scaling ratio, resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts.
ACM can be applied for downscales only from ratio 1 down to
1
64
. ACM results in a scale dependent
DC gain
amplification
, which has to be precorrected by the BCS control of the scaler part.
The phase and scale controlling DTO calculates in 16-bit resolution, controlled by parameters YSCY[15:0] B1H[7:0]
B0H[7:0] and YSCC[15:0] B3H[7:0] B2H[7:0], continuously over the entire filed. A start offset can be applied to the phase
processing by means of the parameters YPY3[7:0] to YPY0[7:0] in BFH[7:0] to BCH[7:0] and YPC3[7:0] to YPC0[7:0] in
BBH[7:0] to B8H[7:0]. The start phase covers the range of
255
32
to
1
32
lines offset.
By programming appropriate, opposite, vertical start phase values (subaddresses B8H to BFH and E8H to EFH)
depending on odd/even field ID of the source video stream and A/B-page cycle, frame ID conversion and field rate
conversion are supported (i.e. de-interlacing, re-interlacing).
Figs 29 and 30 and Tables 15 and 16 describe the use of the offsets.
Remark: The vertical start phase, as well as scaling ratio are defined independently for luminance and
chrominance channel, but must be set to the same values in the actual implementation for accurate 4 : 2 : 2
output processing.
The vertical processing communicates on its input side with the line FIFO buffer. The scale related equations are:
Scaling increment calculation for ACM and LPI mode, downscale and zoom:
YSCY[15:0] and YSCC[15:0]
BCS value to compensate DC gain in ACM mode (contrast and saturation have to be set):
CONT[7:0] A5H[7:0] respectively SATN[7:0] A6H[7:0]
,
or
8.3.3.3
Use of the vertical phase offsets
As described in Section 8.3.1.3, the scaler processing may run randomly over the interlaced input sequence (see
parameters STRC[1:0], FSKP[2:0] and RPTSK). Additionally the interpretation and timing between ITU 656 field ID and
real-time detection by means of the state of H-sync at the falling edge of V-sync may result in different field ID
interpretation.
A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the interlaced input fields are
processed, without regard to the actual scale at the starting point of operation (see Fig.29).
For correct interlaced processing the vertical scaler must be used with respect to the interlace properties of the input
lower integer of
=
1024
Nline_in
Nline_out
------------------------
×
lower integer of
Nline_in
64
×
=
lower integer of
YSCY[15:0]
64
×
=