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Filename:
SAA7115_Datasheet.fm
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page 72
Last edited by H. Lambers
Philips Semiconductors
CS-PD Hamburg
CVIP2
Datasheet
SAA7115
Date:
10/23/01
Version:
0.67
The trigger levels for FAE and FAF are programmable by FFL[1:0] 86H[3:2] (16, 24, 28, full) and FEL[1:0] 86H[1:0] (16,
8, 4, empty).
The state of this flag can be seen on the pins IGP0 or IGP1. The pin mapping is defined by subaddresses 84H and 85H
(see Section 9.5).
8.5.3
T
EXT
FIFO
The data of the internal VBI-data slicer is collected in the text FIFO before the transmission over the I-port is requested
(normally before the video window starts). It is partitioned into two FIFO sections. A complete line is filled into the FIFO
before a data transfer is requested. So normally, one line of text data is ready for transfer, while the next text line is
collected. Thus sliced text data is delivered as a block of qualified data, without any qualification gaps in the byte stream
of the I-port.
The decoded VBI-data is collected in the dedicated VBI-data FIFO. After capture of a line is completed, the FIFO can be
streamed through the image port, preceded by a header, telling line number and standard.
The VBI-data period can be signalled via the sliced data flag on pin IGP0 or IGP1. The decoded VBI-data is lead by the
ITU ancillary data header (SLDOM[4:0] 5DH[5:0] at value > 0H and <8H) or by SAV/EAV codes (SLDOM[4:0] 5DH[5:0]
at value > 0H and bit D3 = 1 ). Similar to the global data qualifier on pin IDQ, the sliced data flag frames the transfer of
sliced VBI data from the first to the last byte and can be taken to distinguish video from sliced VBI data.
The decoded VBI-data are presented in two different data formats, controlled by bit D0 of SLDOM[4:0].
SLDOM[0] = 1: values 00H and FFH will be recoded to even parity values 03H and FCH
SLDOM[0] = 0: values 00H and FFH may occur in the data stream as detected.
8.5.4
V
IDEO
/
TEXT ARBITRATION AND
D
ATA PACKING
(
SUBADDRESS
86H)
Sliced text data and scaled video data are transferred over the same bus, the I-port. The mixed transfer is controlled by
an arbitration circuit and the SLDOM programming.
If the video data are output for the whole field (also during vertical blanking) and the video FIFO does not need to buffer
any output pixel, the text data is inserted after the end of a scaled video line, normally during the horizontal blanking
interval of the video.
8.5.4.1
VBI insertion in SAV/EAV mode (bit SLDOM[3] = ‘1’)
VBI insertion in SAV/EAV mode (bit SLDOM[3] = ‘1’):
Especially for external devices, which do not recognize the ANC framing of the sliced VBI data and which need to use the
SAV/EAV framing, there are now different levels of VBI/video data insertion implemented.
This functionality is controlled by SLDOM [5DH].
Levels of sliced data insertion:
1. SLDOM[4] = 0: video and sliced data, according SLDOM[1], in parallel, VBI data after EAV sequence of a video line
2. SLDOM[4] = 1: sliced data, according SLDOM[1], video output is skipped for these lines
Note:
1.the insertion after EAV and the skipping is only done, if the scaler region overlaps with the LCR defined VBI region.