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參數(shù)資料
| 型號(hào)： | SAA7115 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | PAL/NTSC/SECAM Video Decoder with Adaptive PAL/NTSC Comb Filter, High Performance Scaler, I2C Sliced Data Readback and SQ PIXEL OUTPUT |
| 中文描述： | PAL / NTSC制式/ SECAM視頻解碼器，自適應(yīng)PAL / NTSC制式梳狀濾波器，高性能潔牙機(jī)，刨切的I2C數(shù)據(jù)回讀和SQ像素輸出 |
| 文件頁(yè)數(shù)： | 73/214頁(yè) |
| 文件大?。?/td> | 732K |
| 代理商： | SAA7115 |
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Filename:
SAA7115_Datasheet.fm
Confidential - NDA required
page 73
Last edited by H. Lambers
Philips Semiconductors
CS-PD Hamburg
CVIP2
Datasheet
SAA7115
Date:
10/23/01
Version:
0.67
8.5.4.2
Data Packing (bit IMPAK (86H) and programming of the pulse generator via addr. F5H to FBH)
To make use of the synthesized line locked PLL2 clock and to enable the use of the scaler for a wider application range,
it is now possible to retain the output data of the scaler, until a scaled line can be output as a continuous data package.
This is done via internal trigger pulses, one for each type of scaler output data (video from page A or B or sliced VBI data).
The parameters PGHAPS (video page A), PGHBPS (video page B) andPGHCPS (sliced VBI data) are defining the delay
related to the rising edge of the decoders HREF or of the synthesized HREF (generated by the internal pulse generator,
can take the following equation for the video data streaming.
With
num_buf_pix = number of buffered pixel,
num_buf_lifo = number of pixel buffered in the internal line FIFO
num_buf_fifo = number of pixel buffered in the output FIFO
h_blanking = number of clock cycles during horizontal blanking = 288 (PAL), 276 (NTSC)
sc_run_in = number of clock cycles for scaler running in = about 72 clock cycles for unscaled video
num_buf_pix is about ~= (PGHAPS - h_blanking - sc_run_in) / 2 = num_buf_lifo + num_buf_fifo
Where
num_buf_lifo = 0 for num_buf_pix =< 64 and the maximum value of num_buf_lifo = 768dec
num_buf_fifo = 64 for num_buf_pix > 64
For unscaled video a level around 1/2 of the buffer capacity (num_buf_lifo + num_buf_fifo = 832dec) is recommended.
This leads to a PGHAPS value of about ~= 2 x 416 + h_blanking + sc_run_in = 1192 (PAL case)
for the unscaled case.
To be able to align the EAV sequences for different scales and regions, PGHBPS of page B is a separate parameter.
The number of bytes per line and region defines, whether PGHBPS is to be programmed differently to PGHAPS.
If all data types are to be mixed and a fixed SAV/EAV pattern is needed, the VBI slicer has to become the timing master
for the data packing. To avoid timing shifts in the EAV pattern, the latest point of text line completion defines the earliest
packing timing. This is about 48 clocks before rising edge of the decoders HREF. The slicer data need to be shifted to a
position later than this point. The latest point in time is defined by the internal video skipping procedure (SLDOM[4] =’1’).
Therefore the end of a video line (EAV) need to have a distance of (number of pixels per line) of clock cycles from the
mentioned point of text line completion.
Considering the PLL behaviour and for correct video skipping, the recommendation for this situation and EAV alignment
for 720 pixel per line and PAL (=1728) is:
1728 - (48+56) - 720 - 1448 = -544 = 1184 >= PGHCPS >= 1728 - (48-20) = 1700
PGHAPS = PGHCPS - num_bytes_per_video_line + num_bytes_per_VBI_package = e.g. 1700 - 1448 + 56 = 308dec
For other clock rates than 27 MHz, the mentioned values need to be scaled according to the clock relations, e.g.
24.545454 MHz would give
1560 - 94 - 640 - 1288 = -462 = 1098 >= PGHCPS >= 1560 - 25 = 1535
PGHAPS = e.g. 500 - 1288 + 51 = -737 = 823dec
8.5.5
D
ATA STREAM CODING AND REFERENCE SIGNAL GENERATION
(
SUBADDRESSES
84H, 85H
AND
93H)
As H and V reference signals are logic 1, active gate signals are generated, which frame the transfer of the valid output
data. As an alternative to the gates, H and V trigger pulses are generated on the rising edges of the gates.
Due to the dynamic FIFO behaviour of the complete scaler path, the output signal timing has no fixed timing relationship
to the real-time input video stream. So fixed propagation delays, in terms of clock cycles, related to the analog input
cannot be defined.
The data stream is accompanied by a data qualifier. ITU 656 like codes need to be activated by means of the bit ICODE
set to ‘1’.
The behaviour during non qualified clock cycles is defined by the bit INS80 [93H[6]].
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| SAA7116H | Video Converter Circuit |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7115AHL/V1 | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115AHL/V1,518 | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115AHL/V1,557 | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115AHL/V1-T | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115HL/V1 | 制造商:NXP Semiconductors 功能描述:IC VIDEO DECODR DIGITAL 100 |
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