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參數(shù)資料
| 型號(hào)： | SAA7115 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | PAL/NTSC/SECAM Video Decoder with Adaptive PAL/NTSC Comb Filter, High Performance Scaler, I2C Sliced Data Readback and SQ PIXEL OUTPUT |
| 中文描述： | PAL / NTSC制式/ SECAM視頻解碼器，自適應(yīng)PAL / NTSC制式梳狀濾波器，高性能潔牙機(jī)，刨切的I2C數(shù)據(jù)回讀和SQ像素輸出 |
| 文件頁(yè)數(shù)： | 80/214頁(yè) |
| 文件大小： | 732K |
| 代理商： | SAA7115 |
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Pemnr
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Filename:
SAA7115_Datasheet.fm
Confidential - NDA required
page 80
Last edited by H. Lambers
Philips Semiconductors
CS-PD Hamburg
CVIP2
Datasheet
SAA7115
Date:
10/23/01
Version:
0.67
8.6.1
S
QUARE
P
IXEL
C
LOCK
G
ENERATION
The SAA7115 is capable to output video data especially in Square Pixel formats. i.e.:
PAL video line (625 lines per frame) is output with 768/176 continuous active/inactive video pixel at 29.5 MHz clock
frequency
NTSC Video line(525 lines per frame) is output with 640/140 continuous active/inactive video pixel at 24.54 MHz clock
frequency.
To generate the clock which allows a continuous data stream at the image port the SAA7115 has implemented the
second analog PLL (CGC2) which is stimulated by the line locked second digital PLL (PLL2, alias “Square Pixel” PLL).
TheCGC2output clockdrivestheScaler BackendandthePulseGeneratorto delivervideodatawithSquarePixelformat
at the I-Port. To avoid Scaler FIFO overflows/underruns the pixel clock must be phase aligned to the video input signal.
Hence the reference of the second digital PLL (PLL2) is a horizontal reference signal obtained from the combfilter
decoder or the X-Port input XRH (controlled by SPHSEL, register address F1 H [D1]).
Only the square pixel clock frequencies of 29.5 MHz and 24.5454 MHz are targeted for driving the scaler backend with
PLL2 / CGC2.
8.6.1.1
The second PLL (PLL2)
The second PLL (PLL2) consists of a discrete time oscillator (DTO), a phase detector which computes the phase error
once per video line while taking into account the current DTO phase and a PI -Loop Filter with programmable P/I
coefficients.
If the phase error become less then a programmed locking threshold value SPTHRM [3:0] (register address FF H [3:0])
for a period of time defined number of lines programmed in SPTHRL [3:0] register (register address FF H [7:4]), the PLL2
indicates the status locked. If the PLL is locked, a status register SPLOCK (register address F1H [0]) is set.
The PLL2 is controlled by the following settings:
Number of target clock cycles per line divided by 4 (SPLPL, register addresses F1 h [D0], F0 H [D7:D0]
Nominal DTO increment (SPNINC, register addresses F3 H [D7:D0], F2 H [D7:D0]):
The nominal Increment is basic clock frequency setting for PLL2 and hence for CGC2 clock output (CGC2frequency,
in scaler backend clock generation mode). If PLL2 is opened it is the only parameter which defines the defines the
clock frequency. It depends on the crystal frequency (32.11 MHz or 24.576 MHz) and is calculated as:
PLL2 operation mode (SPMOD, register address F1 H [D3:D2]):
– PLL-closed (normal operation mode, SPMOD = 01 bin):
This is the normal operation mode of the second PLL (PLL2): the nominal increment plus the content of loop filter
define the output (CGC2) frequency.
– Synthesize Clock Mode (SPMOD = 00 bin):
The PLL2 is opened and hence the generated clock frequency at CGC2 output depends only on the nominal
increment defined by the register SPNINC. The contribution of the loop filter is disabled. The I and P proportion of
the loop filter is set to zero.
– PLL-hold (SPMOD = 10 bin):
The CGC2 output keeps the same clock frequency which was generated when entering this mode. In this mode
content of the loop filter of PLL2 will be frozen.
– PLL-Re-Sync (SPMOD = 11 bin)
The phase detector of PLL2 is continuously re-synchronized to the selected horizontal reference signal controlled
by SPHSEL. The remaining phase error is fed into the loop filter.
Loop Filter Mode (P/I parameter selection; SPPI, register address F1 H [D7:D4]):
SPINC
integer
4 XTALfrequency
2
16
=
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| SAA7116 | Digital Video to PCI Interface |
| SAA7116H | Video Converter Circuit |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7115AHL/V1 | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115AHL/V1,518 | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115AHL/V1,557 | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115AHL/V1-T | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115HL/V1 | 制造商:NXP Semiconductors 功能描述:IC VIDEO DECODR DIGITAL 100 |
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