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Filename:
SAA7115_Datasheet.fm
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page 209
Last edited by H. Lambers
Philips Semiconductors
CS-PD Hamburg
CVIP2
Datasheet
SAA7115
Date:
10/23/01
Version:
0.67
17.4.1
E
XAMPLES
Table 187
Example configurations
EXAMPLE
NUMBER
SCALER SOURCE AND REFERENCE EVENTS
INPUT
WINDOW
720
×
240 720
×
240 prsc = 1;
OUTPUT
WINDOW
SCALE
RATIOS
1
analog input to 8-bit I-port output, with SAV/EAV codes and
X-port; acquisition trigger at rising edge vertical and rising
edge horizontal reference signal; ‘1’ active H and V-gates on
IGPH and IGPV, IGP0 = field ID, IGP1 = sliced VBI data flag,
IMPAK = ‘1’ = the pulse generator need to be programmed
(addr. 0xF5 to 0xFB)
IDQ qualifier logic 1 active
window definitions and scale ratio according SQP NTSC-M
analog input to 8-bit I-port output, with SAV/EAV codes and
‘8010’ blanking, 8-bit serial byte stream decoder output at
X-port; acquisition trigger at rising edge vertical and rising
edge horizontal reference signal; ‘1’ active H and V-gates on
IGPH and IGPV, IGP0 = field ID, IGP1 = sliced VBI data flag,
IMPAK = ‘1’ = the pulse generator need to be programmed
(addr. 0xF5 to 0xFB)
PLL2 clock used (ICKS[1:0] = 2),
refer to section 17.5 , Example 2
IDQ qualifier logic 1 active
window definitions and scale ratio according SQP PAL-BG
analog input to 16-bit output, without SAV/EAV codes, Y on
I-port, C
B
-C
R
on H-port and decoder output at X-port;
acquisition trigger at rising edge vertical and rising edge
horizontal reference signal; ‘1’ active H-gate and V-sync on
IGPH and IGPV, IGP0= field ID, IGP1 = filled flag,
IMPAK = ‘1’ = the pulse generator need to be programmed
(addr. 0xF5 to 0xFB)
PLL2 clock used (ICKS[1:0] = 2)
refer to sect.17.5 , Example 3
IDQ = CREF like qualifier at (PLL2 clock )/2 data rate
X-port input 8 bit with SAV/EAV codes, no reference signals on
XRH and XRV, XCLK as gated clock; field detection and
acquisition trigger on different events; acquisition triggers at
falling edge vertical and rising edge horizontal; I-port output
8 bit with SAV/EAV codes like example number 1
X-port and H-port for 16-bit Y-CB-CR 4 : 2 : 2 input (if no 16-bit
output selected); XRH and XRV as references; field detection
and acquisition trigger at falling edge vertical and rising edge
horizontal; I-port output 8 bit with SAV/EAV codes, but Yonly
output
fisc = 1;
vsc = 1
2
704
×
240 640
×
240 prsc = 1;
fisc = 1.1;
vsc = 1
3
704
×
288 768
×
288 prsc = 1;
fisc = 0.91667;
vsc = 1
4
720
×
240 352
×
288 prsc = 2;
fisc = 1.022;
vsc = 0.8333
5
720
×
288 200
×
80
prsc = 2;
fisc = 1.8;
vsc = 3.6