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參數(shù)資料
| 型號(hào)： | SAA7115 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | PAL/NTSC/SECAM Video Decoder with Adaptive PAL/NTSC Comb Filter, High Performance Scaler, I2C Sliced Data Readback and SQ PIXEL OUTPUT |
| 中文描述： | PAL / NTSC制式/ SECAM視頻解碼器，自適應(yīng)PAL / NTSC制式梳狀濾波器，高性能潔牙機(jī)，刨切的I2C數(shù)據(jù)回讀和SQ像素輸出 |
| 文件頁(yè)數(shù)： | 60/214頁(yè) |
| 文件大?。?/td> | 732K |
| 代理商： | SAA7115 |
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Pemnr
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Filename:
SAA7115_Datasheet.fm
Confidential - NDA required
page 60
Last edited by H. Lambers
Philips Semiconductors
CS-PD Hamburg
CVIP2
Datasheet
SAA7115
Date:
10/23/01
Version:
0.67
8.3.2.2
Horizontal fine scaling (variable phase delay filter; subaddresses A8H to AFH and D8H to DFH)
The horizontal fine scaling (VPD) should operate at scaling ratios between
1
2
and 2 (0.8 and 1.6), but can also be used
for direct scaling in the range from
1
7.999
to (theoretical) zoom 3.5 (restriction due to the internal data path architecture),
without prescaler.
In combination with the prescaler a compromise between sharpness impression and alias can be found, which is signal
source and application dependent.
For the luminance channel a filter structure with 10 taps is implemented, and for the chrominance a filter with 4 taps.
Luminance and chrominance scale increments (XSCY[12:0] A9H[4:0]A8H[7:0] and XSCC[12:0] ADH[4:0]ACH[7:0]) are
defined independently, but must be set in a 2 : 1 relationship in the actual data path implementation. The phase offsets
XPHY[7:0] AAH[7:0] and XPHC[7:0] AEH[7:0] can be used to shift the sample phases slightly. XPHY[7:0] and XPHC[7:0]
covers the phase offset range 7.999T to
1
32
T. The phase offsets should also be programmed in a 2 : 1 ratio.
The underlying phase controlling DTO has a 13-bit resolution.
According to the equations
and
the VPD covers the scale range from 0.125 to zoom 3.5. VPD acts equivalent to a polyphase filter with 64 possible
phases. In combination with the prescaler, it is possible to get very accurate samples from a highly anti-aliased integer
downscaled input picture.
8.3.3
V
ERTICAL SCALING
The vertical scaler of the SAA7115 consists of a line FIFO buffer for line repetition and the vertical scaler block, which
implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64
down to icon size
1
64
. The vertical scaler is located between the BCS and horizontal fine scaler, so that the BCS can be
used to compensate the DC gain amplification of the ACM mode (see Section 8.3.3.2) as the internal RAMs are only 8-bit
wide.
8.3.3.1
Line FIFO buffer (subaddresses 91H, B4H and C1H, E4H)
The line FIFO buffer is a dual ported RAM structure for 768 pixels, with asynchronous write and read access. The line
buffer can be used for various functions, but not all functions may be available simultaneously.
The line buffer can buffer a complete unscaled active video line or more than one shorter lines (only for non-mirror mode),
for selective repetition for vertical zoom-up.
For zooming up 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry
for calculation.
For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling scheme (MPEG, video phone, Indeo YUV-9) to ITU like sampling
scheme 4 : 2 : 2, the chrominance line buffer is read twice or four times, before being refilled again by the source. It has
to be preserved by means of the input acquisition window definition, so that the processing starts with a line containing
luminance and chrominance information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits FSC[2:1] 91H[2:1] define the distance
between the Y/C lines. In the case of 4 : 2 : 2 and 4 : 1 : 1 FSC2 and FSC1 have to be set to ‘00’.
The line buffer can also be used for mirroring, i.e. for flipping the image left to right, for the vanity picture in video phone
applications (bit YMIR[B4H[4]]). In mirror mode only one active prescaled line can be held in the FIFO at a time.
The line buffer can be utilized as an excessive pipeline buffer for discontinuous and variable rate transfer conditions at
the expansion port or image port.
Remark to 4 : X : 0 input from X-port
: These input streams need to look like regular 4:2:2 input and are formatted to
the internal 16 bit YUV format. At it’s input port the line fifo only ignores 1 of 2, resp. 3 of 4 chrominance lines, where FSC
defines the skipping sequence.
XSCY[12:0]
1024
Npix_in
XPSC[5:0]
---------------------------
×
1
Npix_out
-----------------------
×
=
XSCC[12:0]
XSC2
=
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| SAA7116 | Digital Video to PCI Interface |
| SAA7116H | Video Converter Circuit |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7115AHL/V1 | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115AHL/V1,518 | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115AHL/V1,557 | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115AHL/V1-T | 功能描述:視頻 IC 9-BIT VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7115HL/V1 | 制造商:NXP Semiconductors 功能描述:IC VIDEO DECODR DIGITAL 100 |
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