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SAA7115_Datasheet.fm
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page 92
Last edited by H. Lambers
Philips Semiconductors
CS-PD Hamburg
CVIP2
Datasheet
SAA7115
Date:
10/23/01
Version:
0.67
Table 34
Clock and real-time synchronization signals
9.4
Video expansion port (X-port)
The expansion port can be used either to output eight or ten bit video from the combfilter decoder directly or to receive
video data from other external digital video sources such as MPEG decoder for output at the image port (I-port) whilst.
The expansion port consists of three main groupings of signals:
8-bit dithered or 10-bit data output of component video Y-C
B
-C
R
4 : 2 : 2, i.e. in C
B
-Y-C
R
-Y, sequence. In 10-bit wide
video mode the two data LSB’s are output on the XRH and XRV signal lines.
Exceptionally raw video samples (e.g. ADC test).
8-bit data input of component video Y-C
B
-C
R
4 : 2 : 2, i.e. C
B
-Y-C
R
-Y, byte serial. In input mode optionally the data bus
can be extended to 16-bit by pins HPD7 to HPD0. In this mode XPD [7:0] carries the luminance data and HPD [7:0]
carries the Chrominance data.
Clock, synchronization and auxiliary I/O signals, accompanying the data stream.
The data transfers through the expansion port represent a single D1 port, with half duplex mode. The SAV and EAV
codes may be inserted optionally for data input (controlled by bit XCODE (92H[3])). The input/output direction is switched
for complete fields only.
SYMBOL
PIN
I/O
DESCRIPTION
BIT
Crystal oscillator
XTALI
XTALO
XTOUT
7
6
4
I
input for crystal oscillator or reference clock
output of crystal oscillator
reference (crystal) clock output drive (optional)
O
O
XTOUTE (14H[3])
Real-time signals (RT port)
LLC
28
O
line-locked clock, nominal 27 MHz, double pixel clock locked to the
selected video input signal, for backward compatibility only, do not use
for new applications
line-locked pixel clock, nominal 13.5 MHz, for backward compatibility
only, do not use for new applications
real-time control output, transfers real-time status information
supporting RTC level 3.1 (see document “RTC Functional Description”,
available on request)
LLC2
29
O
RTCO
36
O
I
Strapping during reset determines the I
2
C read/write addresses
address.
-
RTS0
34
O
real-time status information line 0, can be programmed to carry various
real-time information (see Table 70)
real-time status information line 1, can be programmed to carry various
real-time information (see Table 71)
RTSE0[3:0]
(12H[3:0])
RTSE1[3:0]
(12H[7:4])
RTS1
35
O