
96
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
Table 15.6 Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
0031h
Major version number, ASCII
44h
0034h
Minor version number, ASCII
45h
0100h
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Technology (Bits 5-2) 0100 = 0.11 μm
46h
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
0000h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
0008h
Sector Protect/Unprotect scheme
08 = Advanced Sector Protection
4Ah
00F3h (WS256N)
007Bh (WS128N)
Simultaneous Operation
Number of Sectors in all banks except boot bank
4Bh
0001h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word
Page
4Dh
0085h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh
0095h
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh
0001h
Top/Bottom Boot Sector Flag
0001h = Dual Boot Device
50h
0001h
Program Suspend. 00h = not supported
51h
0001h
Unlock Bypass
00 = Not Supported, 01= Supported
52h
0007h
Secured Silicon Sector (Customer OTP Area) Size 2
N
bytes
53h
0014h
Hardware Reset Low Time-out during an embedded algorithm to read
mode Maximum 2
N
ns
54h
0014h
Hardware Reset Low Time-out not during an embedded algorithm to read
mode Maximum 2
N
ns
55h
0005h
Erase Suspend Time-out Maximum 2
N
ns
56h
0005h
Program Suspend Time-out Maximum 2
N
ns
57h
0010h
Bank Organization: X = Number of banks
58h
0013h (WS256N)
000Bh (WS128N)
Bank 0 Region Information. X = Number of sectors in bank
59h
0010h (WS256N)
0008h (WS128N)
Bank 1 Region Information. X = Number of sectors in bank