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參數(shù)資料
| 型號： | S71WS512NC0BAWA62 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP） |
| 文件頁數(shù)： | 95/188頁 |
| 文件大?。?/td> | 2252K |
| 代理商： | S71WS512NC0BAWA62 |
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September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
93
A d v a n c e I n f o r m a t i o n
Table 15.2 Sector Protection Commands
Command Sequence
( Notes)
Command Set Entry (5)
Program (6, 12)
Read (6)
Command Set Exit (7)
Command Set Entry (5)
Program [0-3] (8)
Read (
9
)
Unlock
Command Set Exit (7)
Command Set Entry (5)
PPB Program (10)
All PPB Erase (10, 11)
PPB Status Read
Command Set Exit (7)
Global
Volatile Sector
Protection
Freeze
(PPB Lock)
Command Set Exit (7)
Command Set Entry (5)
DYB Set
DYB Clear
DYB Status Read
Command Set Exit (7)
C
Bus Cycles ( Notes 1–4)
Third
Addr
Data
555
40
First
Second
Fourth
Addr
Fifth
Sixth
Seventh
Addr
Addr
555
XX
77
XX
555
XX
0...00
00
XX
555
XX
XX
SA
XX
555
XX
BA
XX
555
XX
XX
SA
XX
Data
AA
A0
data
90
AA
A0
PWD0
25
90
AA
A0
80
RD(0)
90
AA
A0
RD(0)
90
AA
A0
A0
RD(0)
90
Addr
2AA
77/00
Data
55
data
Data
Addr
Data
Addr
Data
Data
Lock
Register
Bits
3
2
1
2
3
2
4
7
2
3
2
2
1
2
3
2
1
2
3
2
2
1
2
XX
2AA
00
0...01
00
XX
2AA
SA
00
00
55
Password
Protection
555
60
PWD[0-3]
PWD1
03
00
55
00
30
0...02
00
PWD2
PWD0
0...03
01
PWD3
PWD1
02
PWD2
03
PWD3
00
29
Non-Volatile
Sector
Protection (PPB)
[BA]555
C0
XX
2AA
XX
00
55
00
Command Set Entry (5)
PPB Lock Bit Set
PPB Lock Bit Status Read
[BA]555
50
XX
2AA
SA
SA
00
55
00
01
Volatile Sector
Protection
(DYB)
[BA]555
E0
XX
00
Legend:
X = Don’t care.
RA = Address of the memory location to be read.
PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0].
PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must
be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.
PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must
be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.
PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14.
Notes:
1.
All values are in hexadecimal.
2.
Shaded cells indicate read cycles.
3.
Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
4.
Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
5.
Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
6.
If both the Persistent Protection Mode Locking Bit and the
Password Protection Mode Locking Bit are set at the same time,
the command operation aborts and returns the device to the
default Persistent Sector Protection Mode during 2nd bus cycle.
Note that on all future devices, addresses equal 00h, but is
currently 77h for the WS256N only. See Tables
11.1
and
11.2
for
explanation of lock bits.
7.
Exit command must be issued to reset the device into read
mode; device may otherwise be placed in an unknown state.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20.
PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit
combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If
protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,
DQ2 = 1.
8.
Entire two bus-cycle sequence must be entered for each portion
of the password.
Full address range is required for reading password.
10. See
Figure 11.2
for details.
11. “All PPB Erase” command pre-programs all PPBs before erasure
to prevent over-erasure.
12. The second cycle address for the lock register program operation
is 77 for S29WS256N; however, for WS128N this address is 00.
9.
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