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參數(shù)資料
| 型號： | S71WS512NC0BAWA62 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP） |
| 文件頁數(shù)： | 28/188頁 |
| 文件大?。?/td> | 2252K |
| 代理商： | S71WS512NC0BAWA62 |
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26
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
10 Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshak-
ing, and reset features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command registers (see Tables
15.1
and
15.2
). The command register itself
does not occupy any addressable memory location; rather, it is composed of latches that store
the commands, along with the address and data information needed to execute the command.
The contents of the register serve as input to the internal state machine and the state machine
outputs dictate the function of the device. Writing incorrect address and data values or writing
them in an improper sequence may place the device in an unknown state, in which case the sys-
tem must write the reset command to return the device to the reading array data mode.
10.1
Device Operation Table
The device must be setup appropriately for each operation.
Table 10.1
describes the required
state of each control pin for any particular operation.
Table 10.1 Device Operations
Legend:
L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.
10.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data
is read from one memory location at a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes the data on its outputs to arrive asyn-
chronously with the address on its inputs.
The device defaults to reading array data asynchronously after device power-up or hardware re-
set. To read data from the memory array, the system must first assert a valid address on A
max
–
A0, while driving AVD# and CE# to V
IL
. WE# must remain at V
IH
. The rising edge of AVD# latches
the address. The OE# signal must be driven to V
IL
, once AVD# has been driven to V
IH
. Data is
output on A/DQ15-A/DQ0 pins after the access time (t
OE
) has elapsed from the falling edge of
OE#.
Operation
CE#
OE#
WE#
Addresses
DQ15–0
RESET#
CLK
AVD#
Asynchronous Read - Addresses Latched
L
L
H
Addr In
Data Out
H
X
Asynchronous Read - Addresses Steady State
L
L
H
Addr In
Data Out
H
X
L
Asynchronous Write
L
H
L
Addr In
I/O
H
X
L
Synchronous Write
L
H
L
Addr In
I/O
H
Standby (CE#)
H
X
X
X
HIGH Z
H
X
X
Hardware Reset
X
X
X
X
HIGH Z
L
X
X
Burst Read Operations (Synchronous)
Load Starting Burst Address
L
X
H
Addr In
X
H
Advance Burst to next address with appropriate
Data presented on the Data Bus
L
L
H
X
Burst
Data Out
H
H
Terminate current Burst read cycle
H
X
H
X
HIGH Z
H
X
Terminate current Burst read cycle via RESET#
X
X
H
X
HIGH Z
L
X
X
Terminate current Burst read cycle and start new
Burst read cycle
L
X
H
Addr In
I/O
H
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| S71WS512NC0BAWA63 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
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| S71WS512NC0BAWAJ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
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