
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
89
A d v a n c e I n f o r m a t i o n
14.8.7
Erase and Programming Performance
Notes:
1.
Typical program and erase times assume the following conditions: 25
°
C, 1.8 V V
CC
, 10,000
cycles; checkerboard data pattern.
Under worst case conditions of 90°C, V
CC
= 1.70 V, 100,000 cycles.
Typical chip programming time is considerably less than the maximum chip programming time listed, and is
based on utilizing the Write Buffer.
In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before
erasure.
System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See the
Appendix
for further information on command definitions.
Contact the local sales office for minimum cycling endurance values in specific applications and operating
conditions.
Refer to Application Note “Erase Suspend/Resume Timing” for more details.
Word programming specification is based upon a single word programming operation not utilizing the write
buffer.
The content in this document is Advance information for the S29WS128N. Content in this document is
Preliminary for the S29W256N.
2.
3.
4.
5.
6.
7.
8.
9.
Parameter
Typ (
Note 1
)
Max (
Note 2
)
Unit
Comments
Sector Erase Time
64 Kword
V
CC
0.6
3.5
s
Excludes 00h
programming prior
to erasure (
Note 4
)
16 Kword
V
CC
< 0.15
2
Chip Erase Time
V
CC
153.6 (WS256N)
77.4 (WS128N)
308 (WS256N)
154 (WS128N)
s
ACC
130.6 (WS256N)
65.8 (WS128N)
262 (WS256N)
132 (WS128N)
Single Word Programming Time
(
Note 8
)
V
CC
40
400
μs
ACC
24
240
Effective Word Programming Time
utilizing Program Write Buffer
V
CC
9.4
94
μs
ACC
6
60
Total 32-Word Buffer Programming
Time
V
CC
300
3000
μs
ACC
192
1920
Chip Programming Time (
Note 3
)
V
CC
157.3 (WS256N)
78.6 (WS128N)
314.6 (WS256N)
157.3 (WS128N)
s
Excludes system
level overhead
(
Note 5
)
ACC
100.7 (WS256N)
50.3 (WS128N)
201.3 (WS256N)
100.7 (WS128N)