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參數(shù)資料
| 型號： | S71WS512NC0BAWA62 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP） |
| 文件頁數(shù)： | 22/188頁 |
| 文件大?。?/td> | 2252K |
| 代理商： | S71WS512NC0BAWA62 |
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This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Publication Number
S71WS-N_01
Revision
A
Amendment
4
Issue Date
September 15, 2005
General Description
The Spansion S29WS256/128 are Mirrorbit
TM
Flash products fabricated on 110-nm process technology.
These burst mode Flash devices are capable of performing simultaneous read and write operations with
zero latency on two separate banks using separate data and address pins. These products can operate up
to 80 MHz and use a single V
CC
of 1.7 V to 1.95 V that makes them ideal for today’s demanding wireless
applications requiring higher density, better performance and lowered power consumption.
Distinctive Characteristics
Single 1.8 V read/ program/ erase ( 1.70– 1.95 V)
110 nm MirrorBit Technology
Simultaneous Read/ W rite operation w ith zero
latency
32-w ord W rite Buffer
Sixteen-bank architecture consisting of 16/ 8
Mw ords for W S256N/ 128N, respectively
Four 16 Kw ord sectors at both top and bottom of
memory array
254/ 126 64 Kw ord sectors ( W S256N/ 128N)
Programmable linear ( 8/ 16/ 32) w ith or w ithout
w rap around and continuous burst read modes
Secured Silicon Sector region consisting of 128
w ords each for factory and customer
20-year data retention ( typical)
Cycling Endurance: 100,000 cycles per sector
( typical)
RDY output indicates data available to system
Performance Characteristics
Command set compatible w ith J EDEC ( 42.4)
standard
Hardw are ( W P# ) protection of top and bottom
sectors
Dual boot sector configuration ( top and bottom)
Low V
CC
w rite inhibit
Persistent and Passw ord methods of Advanced
Sector Protection
W rite operation status bits indicate program and
erase operation completion
Suspend and Resume commands for Program and
Erase operations
Unlock Bypass program command to reduce
programming time
Synchronous or Asynchronous program operation,
independent of burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash I nterface ( CFI )
S29WS-N MirrorBit
TM
Flash Family
S29WS256N, S29WS128N
256/128 Megabit (16/8 M x 16 bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst-mode Flash Memory
ADVANCE
INFORMATION
Read Access Times
Speed Option ( MHz)
80
66
54
Max. Synch. Latency, ns (t
IACC
)
80
80
80
Max. Synch. Burst Access, ns (t
BACC
)
9
11.2
13.5
Max. Asynch. Access Time, ns (t
ACC
)
80
80
80
Max CE# Access Time, ns (t
CE
)
80
80
80
Max OE# Access Time, ns (t
OE
)
13.5
13.5
13.5
Current Consumption ( typical values)
Continuous Burst Read @ 80 MHz
38 mA
Simultaneous Operation (asynchronous)
50 mA
Program (asynchronous)
19 mA
Erase (asynchronous)
19 mA
Standby Mode (asynchronous)
20 μA
Typical Program & Erase Times
Single Word Programming
40 μs
Effective Write Buffer Programming (V
CC
) Per Word
9.4 μs
Effective Write Buffer Programming (V
ACC
) Per Word
6 μs
Sector Erase (16 Kword Sector)
150 ms
Sector Erase (64 Kword Sector)
600 ms
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512NC0BAWA63 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BAWA70 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BAWA72 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BAWA73 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BAWAJ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
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