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參數(shù)資料
| 型號： | S71WS512NC0BAWA62 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP） |
| 文件頁數(shù)： | 94/188頁 |
| 文件大?。?/td> | 2252K |
| 代理商： | S71WS512NC0BAWA62 |
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92
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
Table 15.1 Memory Array Commands
Command Sequence
( Notes)
Asynchronous Read (
6
)
Reset (
7
)
Manufacturer ID
Device ID (
9
)
C
Bus Cycles ( Notes 1–5)
Third
Addr
Data
First
Second
Addr
Fourth
Addr
Fifth
Sixth
Addr
RA
XXX
555
555
Data
RD
F0
AA
AA
Data
Data
Addr
Data
Addr
Data
1
1
4
6
A
s
8
)
2AA
2AA
55
55
[BA]555
[BA]555
90
90
[BA]X00
[BA]X01
0001
227E
BA+ X0E
Data
BA+ X0F
2200
Indicator Bits (
10
)
4
555
AA
2AA
55
[BA]555
90
[BA]X03
Data
Program
Write to Buffer (
11
)
Program Buffer to Flash
Write to Buffer Abort Reset (
12
)
Chip Erase
Sector Erase
Erase/Program Suspend (
13
)
Erase/Program Resume (
14
)
Set Configuration Register (
18
)
Read Configuration Register
CFI Query (
15
)
Entry
Program (
16
)
CFI (
16
)
4
6
1
3
6
6
1
1
4
4
1
3
2
1
555
555
SA
555
555
555
BA
BA
555
555
AA
AA
29
AA
AA
AA
B0
30
AA
AA
98
AA
A0
98
2AA
2AA
55
55
555
PA
A0
25
PA
PA
PD
WC
PA
PD
WBL
PD
2AA
2AA
2AA
55
55
55
555
555
555
F0
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
2AA
2AA
55
55
555
555
D0
C6
X00
X00
CR
CR
[BA]555
555
XXX
XXX
U
M
2AA
PA
55
PD
555
20
Reset
2
XXX
90
XXX
00
S
S
Entry
Program (
17
)
Read (
17
)
3
4
1
555
555
00
AA
AA
Data
2AA
2AA
55
55
555
555
88
A0
PA
PD
Exit (
17
)
4
555
AA
2AA
55
555
90
XXX
00
Legend:
X = Don’t care.
RA = Read Address.
RD = Read Data.
PA = Program Address. Addresses latch on the rising edge of the
AVD# pulse or active edge of CLK, whichever occurs first.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
Notes:
1.
See
Table 10.1
for description of bus operations.
2.
All values are in hexadecimal.
3.
Shaded cells indicate read cycles.
4.
Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
5.
Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
6.
No unlock or command cycles required when bank is reading
array data.
7.
Reset command is required to return to reading array data (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high
(while the bank is providing status information) or performing
sector lock/unlock.
8.
The system must provide the bank address. See
Autoselect
section for more information
.
9.
Data in cycle 5 is 2230 (WS256N) or 2231 (WS128N).
10. See
Table 10.9
for indicator bit values.
11. Total number of cycles in the command sequence is determined
by the number of words written to the write buffer.
12. Command sequence resets device for next command after write-
to-buffer operation.
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20.
CR = Configuration Register data bits D15–D0.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
13. System may read and program in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. Erase Resume command is valid only during the Erase Suspend
mode, and requires the bank address.
15. Command is valid when device is ready to read array data or
when device is in autoselect mode. Address equals 55h on all
future devices, but 555h for WS256N/128N.
16. Requires Entry command sequence prior to execution. Unlock
Bypass Reset command is required to return to reading array
data.
17. Requires Entry command sequence prior to execution. Secured
Silicon Sector Exit Reset command is required to exit this mode;
device may otherwise be placed in an unknown state.
18. Requires reset command to configure the Configuration Register.
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