參數(shù)資料
型號： S71PL129JC0BFI9P3
廠商： Spansion Inc.
英文描述： Stacked Multi-Chip Product (MCP) Flash Memory
中文描述： 堆疊式多芯片產(chǎn)品（MCP）的快閃記憶體
文件頁數(shù)： 78/149頁
文件大?。?/td> 2693K
代理商： S71PL129JC0BFI9P3
78
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V V
CC
, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern. All values are subject to change.
2. Under worst case conditions of 90
°
C, V
CC
= 2.7 V, 1,000,000 cycles. All values are subject to change.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See
Table 12
for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
BGA Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control
Table 25. Erase And Programming Performance
Parameter
Typ (
Note 1
)
Max (
Note 2
)
Unit
Comments
Sector Erase Time
0.5
2
sec
Excludes 00h programming
prior to erasure (
Note 4
)
Chip Erase Time
PL129J
135
216
sec
Word Program Time
6
100
μs
Excludes system level
overhead (
Note 5
)
Accelerated Word Program Time
4
60
μs
Chip Program Time
(
Note 3
)
PL129J
50.4
200
sec
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
C
OUT
C
IN2
C
IN3
Input Capacitance
V
IN
= 0
V
OUT
= 0
V
IN
= 0
V
IN
= 0
6.3
7
pF
Output Capacitance
7.0
8
pF
Control Pin Capacitance
5.5
8
pF
WP#/ACC Pin Capacitance
11
12
pF
CE1#
t
CCR
t
CCR
CE2#
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