參數(shù)資料
型號: S71PL129JC0BFI9P3
廠商: Spansion Inc.
英文描述: Stacked Multi-Chip Product (MCP) Flash Memory
中文描述: 堆疊式多芯片產(chǎn)品(MCP)的快閃記憶體
文件頁數(shù): 129/149頁
文件大?。?/td> 2693K
代理商: S71PL129JC0BFI9P3
June 25, 2004 pSRAM_Type02_15A1
Type 2 pSRAM
129
A d v a n c e I n f o r m a t i o n
Notes:
1.
A write occurs during the overlap (t
WP
) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low
with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A
write ends at the earliest transition when CS1# goes high and WE# goes high. The t
WP
is measured from the beginning of
write to the end of write.
2.
t
CW
is measured from the CS1# going low to the end of write.
3.
t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change. t
WR
is applied in case a write ends with CS1# or WE# going
high.
Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled)
Address
Data Valid
UB#, LB#
WE#
Data in
Data out
High-Z
t
WC
t
CW
t
BW
t
WP
t
DH
t
DW
t
WR
t
AW
t
AS
CS1#
CS2
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