參數(shù)資料
型號： S71PL129JC0BFI9P3
廠商： Spansion Inc.
英文描述： Stacked Multi-Chip Product (MCP) Flash Memory
中文描述： 堆疊式多芯片產品（MCP）的快閃記憶體
文件頁數(shù)： 136/149頁
文件大?。?/td> 2693K
代理商： S71PL129JC0BFI9P3
136
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Write Operation
Notes:
1.
Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system
operation, please contact local Spansion representative for the relaxation of 1μs limitation.
2.
Minimum value must be equal or greater than the sum of write pulse (t
CW
, t
WP
or t
BW
) and write recovery time (t
WR
).
3.
Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last.
4.
Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever
occurs last.
5.
Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever
occurs first.
6.
Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first.
7.
t
WPH
minimum is absolute minimum value for device to detect High level. And it is defined at minimum V
IH
level.
8.
If OE# is Low after minimum t
OHCL
, read cycle is initiated. In other words, OE# must be brought to High within 5ns after
CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum t
RC
is met.
9.
If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time
or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum t
RC
is met and data
bus is in High-Z.
Parameter
Symbol
16M
32M
64M
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Write Cycle Time
t
WC
70
1000
65
1000
65
1000
ns
1,2
Address Setup Time
t
AS
0
—
0
—
0
—
ns
3
CE1# Write Pulse Width
t
CW
45
—
40
—
40
—
ns
3
WE# Write Pulse Width
t
WP
45
—
40
—
40
—
ns
3
LB#/UB# Write Pulse Width
t
BW
45
—
40
—
40
—
ns
3
LB#/UB# Byte Mask Setup Time
t
BS
-5
—
–5
—
–5
—
ns
4
LB#/UB# Byte Mask Hold Time
t
BH
-5
—
–5
—
–5
—
ns
5
Write Recovery Time
t
WR
0
—
0
—
0
—
ns
6
CE1# High Pulse Width
t
CP
10
—
12
—
12
—
ns
WE# High Pulse Width
t
WHP
7.5
1000
7.5
1000
7.5
1000
ns
7
LB#/UB# High Pulse Width
t
BHP
10
1000
12
1000
12
1000
ns
Data Setup Time
t
DS
15
—
12
—
12
—
ns
Data Hold Time
t
DH
0
—
0
—
0
—
ns
OE# High to CE1# Low Setup Time for Write
t
OHCL
-5
—
–5
—
–5
—
ns
8
OE# High to Address Setup Time for Write
t
OES
0
—
0
—
0
—
ns
9
LB# and UB# Write Pulse Overlap
t
BWO
30
—
30
—
30
—
ns
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