參數(shù)資料
型號: S71PL129JC0BFI9P3
廠商: Spansion Inc.
英文描述: Stacked Multi-Chip Product (MCP) Flash Memory
中文描述: 堆疊式多芯片產(chǎn)品(MCP)的快閃記憶體
文件頁數(shù): 127/149頁
文件大?。?/td> 2693K
代理商: S71PL129JC0BFI9P3
June 25, 2004 pSRAM_Type02_15A1
Type 2 pSRAM
127
A d v a n c e I n f o r m a t i o n
Notes:
1.
16Mb: A2 ~ A19, 32Mb: A2 ~ A20, 64Mb: A2 ~ A21, 128Mb: A2 ~ A22.
t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device
to device interconnection.
t
OE
(max) is met only when OE# becomes enabled after t
AA
(max).
If invalid address signals shorter than min. t
RC
are continuously repeated for over 4μs, the device needs a normal read
timing (t
RC
) or needs to sustain standby state for min. t
RC
at least once in every 4μs.
Write Timings
Figure 48. Timing Waveform of Page Cycle (Page Mode Only)
Figure 49. Write Cycle #1 (WE# Controlled)
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Valid
Address
Valid
Address
Valid
Address
Valid
Address
Valid
Address
t
PC
t
PA
High Z
A1~A0
DQ15~DQ0
OE#
t
OHZ
t
OE
t
CO
t
AA
CS1#
CS2
Address
1)
Address
CS1#
Data Undefined
UB#, LB#
WE#
Data in
Data out
t
WC
t
CW
t
WR
t
AW
t
BW
t
WP
t
AS
t
DH
t
DW
t
WHZ
t
OW
High-Z
High-Z
Data Valid
CS2
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