參數(shù)資料
型號(hào)： S71PL129JC0BFI9P3
廠商： Spansion Inc.
英文描述： Stacked Multi-Chip Product (MCP) Flash Memory
中文描述： 堆疊式多芯片產(chǎn)品（MCP）的快閃記憶體
文件頁數(shù)： 135/149頁
文件大?。?/td> 2693K
代理商： S71PL129JC0BFI9P3
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
135
A d v a n c e i n f o r m a t i o n
AC Characteristics
(Under Recommended Operating Conditions Unless Otherwise Noted)
Read Operation
Notes:
1.
Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A21. If needed by system
operation, please contact local Spansion representative for the relaxation of 1μs limitation.
2.
Address should not be changed within minimum t
RC
.
3.
The output load 50 pF with 50 ohm termination to V
DD
x 0.5 (16M), The output load 50 pF (32M and 64M).
4.
The output load 5pF.
5.
Applicable to A3 to A21 (32M and 64M) when CE1# is kept at Low.
6.
Applicable only to A0, A1 and A2 (32M and 64M) when CE1# is kept at Low for the page address access.
7.
In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4 μs. In other
words, Page Read Cycle must be closed within 4 μs.
8.
Applicable when at least two of address inputs among applicable are switched from previous state.
9.
t
RC
(min) and t
PRC
(min) must be satisfied.
10. If actual value of t
WHOL
is shorter than specified minimum values, the actual t
AA
of following Read can become longer by the
amount of subtracting the actual value from the specified minimum value.
Parameter
Symbol
16M
32M
64M
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle Time
t
RC
70
1000
65
1000
65
1000
ns
1, 2
CE1# Access Time
t
CE
—
60
—
65
—
65
ns
3
OE# Access Time
t
OE
—
40
—
40
—
40
ns
3
Address Access Time
t
AA
—
60
—
65
—
65
ns
3, 5
LB# / UB# Access Time
t
BA
—
30
—
30
—
30
ns
3
Page Address Access Time
t
PAA
N/A
—
20
—
20
ns
3,6
Page Read Cycle Time
t
PRC
N/A
20
1000
20
1000
ns
1, 6, 7
Output Data Hold Time
t
OH
5
—
5
—
5
—
ns
3
CE1# Low to Output Low-Z
t
CLZ
5
—
5
—
5
—
ns
4
OE# Low to Output Low-Z
t
OLZ
0
—
0
—
0
—
ns
4
LB# / UB# Low to Output Low-Z
t
BLZ
0
—
0
—
0
—
ns
4
CE1# High to Output High-Z
t
CHZ
—
20
—
20
—
20
ns
3
OE# High to Output High-Z
t
OHZ
—
20
—
14
—
14
ns
3
LB# / UB# High to Output High-Z
t
BHZ
—
20
—
20
—
20
ns
3
Address Setup Time to CE1# Low
t
ASC
6
—
–6
—
–6
—
ns
Address Setup Time to OE# Low
t
ASO
10
—
10
—
10
—
ns
Address Invalid Time
t
AX
—
10
—
10
—
10
ns
5, 8
Address Hold Time from CE1# High
t
CHAH
-6
—
–6
—
–6
—
ns
9
Address Hold Time from OE# High
t
OHAH
-6
—
–6
—
–6
—
ns
WE# High to OE# Low Time for Read
t
WHOL
10
1000
12
—
25
—
ns
10
CE1# High Pulse Width
t
CP
10
—
12
—
12
—
ns
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