參數(shù)資料
型號(hào): S29CD016G0JFFM012
廠商: Spansion Inc.
英文描述: 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
中文描述: 32兆位(1米× 32位),16兆位(512k × 32的位),2.5伏,只有突發(fā)模式,雙啟動(dòng),同步讀/寫閃存與VersatileI內(nèi)存/輸出
文件頁(yè)數(shù): 58/87頁(yè)
文件大小: 792K
代理商: S29CD016G0JFFM012
56
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Write Operation Status
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5,
DQ6, DQ7, and RY/BY#.
Table 43
and the following subsections describe the functions of these
bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are discussed first.
DQ7: Data# Polling
The device features a Data# polling flag as a method to indicate to the host system whether the
embedded algorithms are in progress or are complete. During the Embedded Program Algorithm,
an attempt to read the bank in which programming was initiated produces the complement of the
data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to
read the device produces the true last data written to DQ7. Note that DATA# polling returns in-
valid data for the address being programmed or erased.
For example, the data read for an address programmed as 0000 0000 1000 0000b, returns XXXX
XXXX 0XXX XXXXb during an Embedded Program operation. Once the Embedded Program Algo-
rithm is complete, the true data is read back on DQ7. Note that at the instant when DQ7 switches
to true data, the other bits may not yet be true. However, they are all true data on the next read
from the device. Please note that Data# polling may give misleading status when an attempt is
made to write to a protected sector.
For chip erase, the Data# polling flag is valid after the rising edge of the sixth WE# pulse in the
six write pulse sequence. For sector erase, the Data# polling is valid after the last rising edge of
the sector erase WE# pulse. Data# polling must be performed at sector addresses within any of
the sectors being erased and not a sector that is a protected sector. Otherwise, the status may
not be valid. DQ7 = 0 during an Embedded Erase Algorithm (chip erase or sector erase operation),
but returns a
1
after the operation completes because it drops back into read mode.
In asynchronous mode, just prior to the completion of the Embedded Algorithm operations, DQ7
may change asynchronously while OE# is asserted low. (In synchronous mode, ADV# exhibits
this behavior.) The status information may be invalid during the instance of transition from status
information to array (memory) data. An extra validity check is therefore specified in the data poll-
ing algorithm. The valid array data on DQ31–DQ0 is available for reading on the next successive
read attempt.
The Data# polling feature is only active during the Embedded Programming Algorithm, Embedded
Erase Algorithm, Erase Suspend, Erase Suspend-Program mode, or sector erase time-out.
If the user attempts to write to a protected sector, Data# polling is activated for about 1 μs: the
device then returns to read mode, with the data from the protected sector unchanged. If the user
attempts to erase a protected sector, Toggle Bit (DQ6) is activated for about 150 μs; the device
then returns to read mode, without having erased the protected sector.
Table 43
shows the outputs for Data# Polling on DQ7.
Figure 6 on page 57
shows the Data# Poll-
ing algorithm.
Figure 23
shows the timing diagram for synchronous status DQ7 data polling.
RY/BY#: Ready/Busy#
The device provides a RY/BY# open drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or completed. If the output is low, the device is
busy with either a program, erase, or reset operation. If the output is floating, the device is ready
to accept any read/write or erase operation. When the RY/BY# pin is low, the device does not
accept any additional program or erase commands with the exception of the Erase suspend com-
mand. If the device enters Erase Suspend mode, the RY/BY# output is floating. For programming,
the RY/BY# is valid (RY/BY# = 0) after the rising edge of the fourth WE# pulse in the four write
pulse sequence. For chip erase, the RY/BY# is valid after the rising edge of the sixth WE# pulse
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